Skip to content

[LoongArch] Supports FP_TO_SINT operation for fp16 #118303

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 3 commits into from
Dec 5, 2024
Merged

[LoongArch] Supports FP_TO_SINT operation for fp16 #118303

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
8914c54
[LoongArch] Supports FP_TO_SINT operation for fp16
heiher Dec 2, 2024
57d8632
Update test case
heiher Dec 3, 2024
998a308
Rename test case test_half_to_s32_u32
heiher Dec 3, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
11 changes: 8 additions & 3 deletions llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1669,16 +1669,19 @@ SDValue LoongArchTargetLowering::lowerFP_TO_SINT(SDValue Op,
SelectionDAG &DAG) const {

SDLoc DL(Op);
SDValue Op0 = Op.getOperand(0);

if (Op0.getValueType() == MVT::f16)
Op0 = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, Op0);

if (Op.getValueSizeInBits() > 32 && Subtarget.hasBasicF() &&
!Subtarget.hasBasicD()) {
SDValue Dst =
DAG.getNode(LoongArchISD::FTINT, DL, MVT::f32, Op.getOperand(0));
SDValue Dst = DAG.getNode(LoongArchISD::FTINT, DL, MVT::f32, Op0);
return DAG.getNode(LoongArchISD::MOVFR2GR_S_LA64, DL, MVT::i64, Dst);
}

EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits());
SDValue Trunc = DAG.getNode(LoongArchISD::FTINT, DL, FPTy, Op.getOperand(0));
SDValue Trunc = DAG.getNode(LoongArchISD::FTINT, DL, FPTy, Op0);
return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Trunc);
}

Expand Down Expand Up @@ -2872,6 +2875,8 @@ void LoongArchTargetLowering::ReplaceNodeResults(
EVT FVT = EVT::getFloatingPointVT(N->getValueSizeInBits(0));
if (getTypeAction(*DAG.getContext(), Src.getValueType()) !=
TargetLowering::TypeSoftenFloat) {
if (Src.getValueType() == MVT::f16)
Src = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, Src);
SDValue Dst = DAG.getNode(LoongArchISD::FTINT, DL, FVT, Src);
Results.push_back(DAG.getNode(ISD::BITCAST, DL, VT, Dst));
return;
Expand Down
81 changes: 81 additions & 0 deletions llvm/test/CodeGen/LoongArch/fp16-promote.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -378,3 +378,84 @@ define half @freeze_half_poison(half %maybe.poison) nounwind {
%t1 = fadd half %y1, %y1
ret half %t1
}

define signext i32 @test_half_to_s32(half %a) nounwind {
; LA32-LABEL: test_half_to_s32:
; LA32: # %bb.0: # %entry
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(__gnu_h2f_ieee)
; LA32-NEXT: ftintrz.w.s $fa0, $fa0
; LA32-NEXT: movfr2gr.s $a0, $fa0
; LA32-NEXT: ld.w $ra, $sp, 12 # 4-byte Folded Reload
; LA32-NEXT: addi.w $sp, $sp, 16
; LA32-NEXT: ret
;
; LA64-LABEL: test_half_to_s32:
; LA64: # %bb.0: # %entry
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(__gnu_h2f_ieee)
; LA64-NEXT: ftintrz.w.s $fa0, $fa0
; LA64-NEXT: movfr2gr.s $a0, $fa0
; LA64-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; LA64-NEXT: addi.d $sp, $sp, 16
; LA64-NEXT: ret
entry:
%conv = fptosi half %a to i32
ret i32 %conv
}

define zeroext i32 @test_half_to_s32_u32(half %a) nounwind {
; LA32-LABEL: test_half_to_s32_u32:
; LA32: # %bb.0: # %entry
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(__gnu_h2f_ieee)
; LA32-NEXT: ftintrz.w.s $fa0, $fa0
; LA32-NEXT: movfr2gr.s $a0, $fa0
; LA32-NEXT: ld.w $ra, $sp, 12 # 4-byte Folded Reload
; LA32-NEXT: addi.w $sp, $sp, 16
; LA32-NEXT: ret
;
; LA64-LABEL: test_half_to_s32_u32:
; LA64: # %bb.0: # %entry
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(__gnu_h2f_ieee)
; LA64-NEXT: ftintrz.w.s $fa0, $fa0
; LA64-NEXT: movfr2gr.s $a0, $fa0
; LA64-NEXT: bstrpick.d $a0, $a0, 31, 0
; LA64-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; LA64-NEXT: addi.d $sp, $sp, 16
; LA64-NEXT: ret
entry:
%conv = fptosi half %a to i32
ret i32 %conv
}

define i64 @test_half_to_i64(half %a) nounwind {
; LA32-LABEL: test_half_to_i64:
; LA32: # %bb.0: # %entry
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(__gnu_h2f_ieee)
; LA32-NEXT: bl %plt(__fixsfdi)
; LA32-NEXT: ld.w $ra, $sp, 12 # 4-byte Folded Reload
; LA32-NEXT: addi.w $sp, $sp, 16
; LA32-NEXT: ret
;
; LA64-LABEL: test_half_to_i64:
; LA64: # %bb.0: # %entry
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(__gnu_h2f_ieee)
; LA64-NEXT: ftintrz.l.s $fa0, $fa0
; LA64-NEXT: movfr2gr.d $a0, $fa0
; LA64-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; LA64-NEXT: addi.d $sp, $sp, 16
; LA64-NEXT: ret
entry:
%conv = fptosi half %a to i64
ret i64 %conv
}
Loading