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[SPIR-V] Emit OpConstant instead of OpConstantNull to conform to NonSemantic.Shader.DebugInfo.100 DebugTypeBasic's flags definition #118333

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Merged
merged 2 commits into from
Dec 3, 2024
Merged

[SPIR-V] Emit OpConstant instead of OpConstantNull to conform to NonSemantic.Shader.DebugInfo.100 DebugTypeBasic's flags definition #118333

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384938c
emit OpConstant instead of OpConstantNull to conform to NonSemantic.S…
VyacheslavLevytskyy Dec 2, 2024
8ef0fa2
clang-format
VyacheslavLevytskyy Dec 2, 2024
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2 changes: 1 addition & 1 deletion llvm/lib/Target/SPIRV/SPIRVEmitNonSemanticDI.cpp
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Expand Up @@ -268,7 +268,7 @@ bool SPIRVEmitNonSemanticDI::emitGlobalDI(MachineFunction &MF) {
// We aren't extracting any DebugInfoFlags now so we
// emitting zero to use as <id>Flags argument for DebugBasicType
const Register I32ZeroReg =
GR->buildConstantInt(0, MIRBuilder, I32Ty, false);
GR->buildConstantInt(0, MIRBuilder, I32Ty, false, false);

// We need to store pairs because further instructions reference
// the DIBasicTypes and size will be always small so there isn't
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6 changes: 3 additions & 3 deletions llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
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Expand Up @@ -325,8 +325,8 @@ Register SPIRVGlobalRegistry::getOrCreateConstInt(uint64_t Val, MachineInstr &I,

Register SPIRVGlobalRegistry::buildConstantInt(uint64_t Val,
MachineIRBuilder &MIRBuilder,
SPIRVType *SpvType,
bool EmitIR) {
SPIRVType *SpvType, bool EmitIR,
bool ZeroAsNull) {
assert(SpvType);
auto &MF = MIRBuilder.getMF();
const IntegerType *LLVMIntTy =
Expand All @@ -348,7 +348,7 @@ Register SPIRVGlobalRegistry::buildConstantInt(uint64_t Val,
} else {
Register SpvTypeReg = getSPIRVTypeID(SpvType);
MachineInstrBuilder MIB;
if (Val) {
if (Val || !ZeroAsNull) {
MIB = MIRBuilder.buildInstr(SPIRV::OpConstantI)
.addDef(Res)
.addUse(SpvTypeReg);
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3 changes: 2 additions & 1 deletion llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
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Expand Up @@ -509,7 +509,8 @@ class SPIRVGlobalRegistry {

public:
Register buildConstantInt(uint64_t Val, MachineIRBuilder &MIRBuilder,
SPIRVType *SpvType, bool EmitIR = true);
SPIRVType *SpvType, bool EmitIR = true,
bool ZeroAsNull = true);
Register getOrCreateConstInt(uint64_t Val, MachineInstr &I,
SPIRVType *SpvType, const SPIRVInstrInfo &TII,
bool ZeroAsNull = true);
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/SPIRV/debug-info/debug-type-basic.ll
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Expand Up @@ -7,7 +7,7 @@
; CHECK-MIR-DAG: [[type_i32:%[0-9]+\:type]] = OpTypeInt 32, 0
; CHECK-MIR-DAG: [[encoding_signedchar:%[0-9]+\:iid\(s32\)]] = OpConstantI [[type_i32]], 5
; CHECK-MIR-DAG: [[encoding_float:%[0-9]+\:iid\(s32\)]] = OpConstantI [[type_i32]], 3
; CHECK-MIR-DAG: [[flag_zero:%[0-9]+\:iid\(s32\)]] = OpConstantNull [[type_i32]]
; CHECK-MIR-DAG: [[flag_zero:%[0-9]+\:iid\(s32\)]] = OpConstantI [[type_i32]], 0
; CHECK-MIR-DAG: [[str_bool:%[0-9]+\:id\(s32\)]] = OpString 1819242338, 0
; CHECK-MIR-DAG: [[size_8bits:%[0-9]+\:iid\(s32\)]] = OpConstantI [[type_i32]], 8
; CHECK-MIR-DAG: [[encoding_boolean:%[0-9]+\:iid\(s32\)]] = OpConstantI [[type_i32]], 2
Expand Down Expand Up @@ -60,7 +60,7 @@
; CHECK-SPIRV-DAG: [[type_int16:%[0-9]+]] = OpTypeInt 16 0
; CHECK-SPIRV-DAG: [[type_int32:%[0-9]+]] = OpTypeInt 32 0
; CHECK-SPIRV-DAG: [[encoding_signedchar:%[0-9]+]] = OpConstant [[type_int32]] 5
; CHECK-SPIRV-DAG: [[flag_zero:%[0-9]+]] = OpConstantNull [[type_int32]]
; CHECK-SPIRV-DAG: [[flag_zero:%[0-9]+]] = OpConstant [[type_int32]] 0
; CHECK-SPIRV-DAG: [[encoding_float:%[0-9]+]] = OpConstant [[type_int32]] 3
; CHECK-SPIRV-DAG: [[size_8bit:%[0-9]+]] = OpConstant [[type_int32]] 8
; CHECK-SPIRV-DAG: [[encoding_boolean:%[0-9]+]] = OpConstant [[type_int32]] 2
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