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[GISel] Teach computeKnownBitsImpl to handle COPY instructions that change bit width. #118924

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Merged
merged 2 commits into from
Dec 7, 2024
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[GISel] Teach computeKnownBitsImpl to handle COPY instructions that change bit width. #118924

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3e6bc8c
[GISel] Teach computeKnownBitsImpl to handle COPY instructions that c…
topperc Dec 6, 2024
f2ab80d
fixup! Add -o - to test.
topperc Dec 7, 2024
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1 change: 1 addition & 0 deletions llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -253,6 +253,7 @@ void GISelKnownBits::computeKnownBitsImpl(Register R, KnownBits &Known,
// For COPYs we don't do anything, don't increase the depth.
computeKnownBitsImpl(SrcReg, Known2, DemandedElts,
Depth + (Opcode != TargetOpcode::COPY));
Known2 = Known2.anyextOrTrunc(BitWidth);
Known = Known.intersectWith(Known2);
// If we reach a point where we don't know anything
// just stop looking through the operands.
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36 changes: 36 additions & 0 deletions llvm/test/CodeGen/RISCV/GlobalISel/knownbits-copy-crash.mir
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@@ -0,0 +1,36 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=riscv64 -mattr=+zbb,+f -run-pass=instruction-select %s -o - | FileCheck %s

---
name: foo
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: foo
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, %6, %bb.1
; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[PHI]], 0
; CHECK-NEXT: [[FCVT_S_W:%[0-9]+]]:fpr32 = nofpexcept FCVT_S_W [[ADDIW]], 7
; CHECK-NEXT: [[FCVT_W_S:%[0-9]+]]:gpr = nofpexcept FCVT_W_S [[FCVT_S_W]], 1
; CHECK-NEXT: PseudoBR %bb.1
bb.1:
%7:gprb(s64) = G_CONSTANT i64 0
%3:gprb(s32) = G_TRUNC %7(s64)
bb.2:
%0:gprb(s32) = G_PHI %3(s32), %bb.1, %2(s32), %bb.2
%6:gprb(s64) = G_SEXT %0(s32)
%1:fprb(s32) = G_SITOFP %6(s64)
%5:gprb(s64) = G_FCVT_W_RV64 %1(s32), 1
%2:gprb(s32) = G_TRUNC %5(s64)
G_BR %bb.2
...
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