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[AMDGPU] New aliases v_add3_nc_u32 and v_xor_add_u32 #118970

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Merged
merged 1 commit into from
Dec 6, 2024
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Merged

[AMDGPU] New aliases v_add3_nc_u32 and v_xor_add_u32 #118970

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5 changes: 5 additions & 0 deletions llvm/lib/Target/AMDGPU/VOP3Instructions.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1750,6 +1750,11 @@ defm V_OR_B16_fake16 : VOP3Only_Realtriple_t16_gfx11_gfx12<0x363, "v_or_b1
defm V_XOR_B16_t16 : VOP3Only_Realtriple_t16_gfx11_gfx12<0x364, "v_xor_b16">;
defm V_XOR_B16_fake16 : VOP3Only_Realtriple_t16_gfx11_gfx12<0x364, "v_xor_b16">;

let AssemblerPredicate = isGFX11Plus in {
def : AMDGPUMnemonicAlias<"v_add3_nc_u32", "v_add3_u32">;
def : AMDGPUMnemonicAlias<"v_xor_add_u32", "v_xad_u32">;
}

//===----------------------------------------------------------------------===//
// GFX10.
//===----------------------------------------------------------------------===//
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6 changes: 6 additions & 0 deletions llvm/test/MC/AMDGPU/gfx11_asm_vop3_alias.s
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Expand Up @@ -6,3 +6,9 @@ v_cvt_pknorm_i16_f16 v5, v1, v2

v_cvt_pknorm_u16_f16 v5, v1, v2
// GFX11: v_cvt_pk_norm_u16_f16 v5, v1, v2 ; encoding: [0x05,0x00,0x13,0xd7,0x01,0x05,0x02,0x00]

v_add3_nc_u32 v5, v1, v2, s3
// GFX11: v_add3_u32 v5, v1, v2, s3 ; encoding: [0x05,0x00,0x55,0xd6,0x01,0x05,0x0e,0x00]

v_xor_add_u32 v5, v1, v2, s3
// GFX11: v_xad_u32 v5, v1, v2, s3 ; encoding: [0x05,0x00,0x45,0xd6,0x01,0x05,0x0e,0x00]
6 changes: 6 additions & 0 deletions llvm/test/MC/AMDGPU/gfx12_asm_vop3_aliases.s
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Expand Up @@ -47,3 +47,9 @@ v_cvt_pknorm_i16_f16 v5, v1, v2

v_cvt_pknorm_u16_f16 v5, v1, v2
// GFX12: v_cvt_pk_norm_u16_f16 v5, v1, v2 ; encoding: [0x05,0x00,0x13,0xd7,0x01,0x05,0x02,0x00]

v_add3_nc_u32 v5, v1, v2, s3
// GFX12: v_add3_u32 v5, v1, v2, s3 ; encoding: [0x05,0x00,0x55,0xd6,0x01,0x05,0x0e,0x00]

v_xor_add_u32 v5, v1, v2, s3
// GFX12: v_xad_u32 v5, v1, v2, s3 ; encoding: [0x05,0x00,0x45,0xd6,0x01,0x05,0x0e,0x00]
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