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Merged
merged 6 commits into from
Jan 9, 2025
Merged

[AArch64] Combine and and lsl into ubfiz #118974

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c41f665
[AArch64] Combine and and lsl into ubfiz
c-rhodes Dec 6, 2024
5099321
Move to target DAG-combine
c-rhodes Dec 13, 2024
69be811
Exclude more uses of SHL that might be combined
c-rhodes Dec 13, 2024
fdbe823
address comments
c-rhodes Dec 13, 2024
f0cbfdd
canonicalize after legalization
c-rhodes Jan 8, 2025
ed9338a
address comments
c-rhodes Jan 8, 2025
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41 changes: 41 additions & 0 deletions llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1140,6 +1140,8 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,

setTargetDAGCombine(ISD::SCALAR_TO_VECTOR);

setTargetDAGCombine(ISD::SHL);

// In case of strict alignment, avoid an excessive number of byte wide stores.
MaxStoresPerMemsetOptSize = 8;
MaxStoresPerMemset =
Expand Down Expand Up @@ -26365,6 +26367,43 @@ performScalarToVectorCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
return NVCAST;
}

/// If the operand is a bitwise AND with a constant RHS, and the shift has a
/// constant RHS and is the only use, we can pull it out of the shift, i.e.
///
/// (shl (and X, C1), C2) -> (and (shl X, C2), (shl C1, C2))
///
/// We prefer this canonical form to match existing isel patterns.
static SDValue performSHLCombine(SDNode *N,
TargetLowering::DAGCombinerInfo &DCI,
SelectionDAG &DAG) {
if (DCI.isBeforeLegalizeOps())
return SDValue();

SDValue Op0 = N->getOperand(0);
if (Op0.getOpcode() != ISD::AND || !Op0.hasOneUse())
return SDValue();

SDValue C1 = Op0->getOperand(1);
SDValue C2 = N->getOperand(1);
if (!isa<ConstantSDNode>(C1) || !isa<ConstantSDNode>(C2))
return SDValue();

// Might be folded into shifted op, do not lower.
if (N->hasOneUse()) {
unsigned UseOpc = N->user_begin()->getOpcode();
if (UseOpc == ISD::ADD || UseOpc == ISD::SUB || UseOpc == ISD::SETCC ||
UseOpc == AArch64ISD::ADDS || UseOpc == AArch64ISD::SUBS)
return SDValue();
}

SDLoc DL(N);
EVT VT = N->getValueType(0);
SDValue X = Op0->getOperand(0);
SDValue NewRHS = DAG.getNode(ISD::SHL, DL, VT, C1, C2);
SDValue NewShift = DAG.getNode(ISD::SHL, DL, VT, X, C2);
return DAG.getNode(ISD::AND, DL, VT, NewShift, NewRHS);
}

SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
DAGCombinerInfo &DCI) const {
SelectionDAG &DAG = DCI.DAG;
Expand Down Expand Up @@ -26710,6 +26749,8 @@ SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
return performCTLZCombine(N, DAG, Subtarget);
case ISD::SCALAR_TO_VECTOR:
return performScalarToVectorCombine(N, DCI, DAG);
case ISD::SHL:
return performSHLCombine(N, DCI, DAG);
}
return SDValue();
}
Expand Down
101 changes: 47 additions & 54 deletions llvm/test/CodeGen/AArch64/const-shift-of-constmasked.ll
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Expand Up @@ -190,8 +190,7 @@ define i8 @test_i8_224_mask_ashr_6(i8 %a0) {
define i8 @test_i8_7_mask_shl_1(i8 %a0) {
; CHECK-LABEL: test_i8_7_mask_shl_1:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0x7
; CHECK-NEXT: lsl w0, w8, #1
; CHECK-NEXT: ubfiz w0, w0, #1, #3
; CHECK-NEXT: ret
%t0 = and i8 %a0, 7
%t1 = shl i8 %t0, 1
Expand All @@ -200,8 +199,7 @@ define i8 @test_i8_7_mask_shl_1(i8 %a0) {
define i8 @test_i8_7_mask_shl_4(i8 %a0) {
; CHECK-LABEL: test_i8_7_mask_shl_4:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0x7
; CHECK-NEXT: lsl w0, w8, #4
; CHECK-NEXT: ubfiz w0, w0, #4, #3
; CHECK-NEXT: ret
%t0 = and i8 %a0, 7
%t1 = shl i8 %t0, 4
Expand Down Expand Up @@ -229,8 +227,8 @@ define i8 @test_i8_7_mask_shl_6(i8 %a0) {
define i8 @test_i8_28_mask_shl_1(i8 %a0) {
; CHECK-LABEL: test_i8_28_mask_shl_1:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0x1c
; CHECK-NEXT: lsl w0, w8, #1
; CHECK-NEXT: lsl w8, w0, #1
; CHECK-NEXT: and w0, w8, #0x38
; CHECK-NEXT: ret
%t0 = and i8 %a0, 28
%t1 = shl i8 %t0, 1
Expand All @@ -239,8 +237,8 @@ define i8 @test_i8_28_mask_shl_1(i8 %a0) {
define i8 @test_i8_28_mask_shl_2(i8 %a0) {
; CHECK-LABEL: test_i8_28_mask_shl_2:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0x1c
; CHECK-NEXT: lsl w0, w8, #2
; CHECK-NEXT: lsl w8, w0, #2
; CHECK-NEXT: and w0, w8, #0x70
; CHECK-NEXT: ret
%t0 = and i8 %a0, 28
%t1 = shl i8 %t0, 2
Expand All @@ -249,8 +247,8 @@ define i8 @test_i8_28_mask_shl_2(i8 %a0) {
define i8 @test_i8_28_mask_shl_3(i8 %a0) {
; CHECK-LABEL: test_i8_28_mask_shl_3:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0x1c
; CHECK-NEXT: lsl w0, w8, #3
; CHECK-NEXT: lsl w8, w0, #3
; CHECK-NEXT: and w0, w8, #0xe0
; CHECK-NEXT: ret
%t0 = and i8 %a0, 28
%t1 = shl i8 %t0, 3
Expand All @@ -259,8 +257,8 @@ define i8 @test_i8_28_mask_shl_3(i8 %a0) {
define i8 @test_i8_28_mask_shl_4(i8 %a0) {
; CHECK-LABEL: test_i8_28_mask_shl_4:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0xc
; CHECK-NEXT: lsl w0, w8, #4
; CHECK-NEXT: lsl w8, w0, #4
; CHECK-NEXT: and w0, w8, #0xc0
; CHECK-NEXT: ret
%t0 = and i8 %a0, 28
%t1 = shl i8 %t0, 4
Expand All @@ -270,8 +268,8 @@ define i8 @test_i8_28_mask_shl_4(i8 %a0) {
define i8 @test_i8_224_mask_shl_1(i8 %a0) {
; CHECK-LABEL: test_i8_224_mask_shl_1:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0x60
; CHECK-NEXT: lsl w0, w8, #1
; CHECK-NEXT: lsl w8, w0, #1
; CHECK-NEXT: and w0, w8, #0xc0
; CHECK-NEXT: ret
%t0 = and i8 %a0, 224
%t1 = shl i8 %t0, 1
Expand Down Expand Up @@ -465,8 +463,7 @@ define i16 @test_i16_65024_mask_ashr_10(i16 %a0) {
define i16 @test_i16_127_mask_shl_1(i16 %a0) {
; CHECK-LABEL: test_i16_127_mask_shl_1:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0x7f
; CHECK-NEXT: lsl w0, w8, #1
; CHECK-NEXT: ubfiz w0, w0, #1, #7
; CHECK-NEXT: ret
%t0 = and i16 %a0, 127
%t1 = shl i16 %t0, 1
Expand All @@ -475,8 +472,7 @@ define i16 @test_i16_127_mask_shl_1(i16 %a0) {
define i16 @test_i16_127_mask_shl_8(i16 %a0) {
; CHECK-LABEL: test_i16_127_mask_shl_8:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0x7f
; CHECK-NEXT: lsl w0, w8, #8
; CHECK-NEXT: ubfiz w0, w0, #8, #7
; CHECK-NEXT: ret
%t0 = and i16 %a0, 127
%t1 = shl i16 %t0, 8
Expand Down Expand Up @@ -504,8 +500,8 @@ define i16 @test_i16_127_mask_shl_10(i16 %a0) {
define i16 @test_i16_2032_mask_shl_3(i16 %a0) {
; CHECK-LABEL: test_i16_2032_mask_shl_3:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0x7f0
; CHECK-NEXT: lsl w0, w8, #3
; CHECK-NEXT: lsl w8, w0, #3
; CHECK-NEXT: and w0, w8, #0x3f80
; CHECK-NEXT: ret
%t0 = and i16 %a0, 2032
%t1 = shl i16 %t0, 3
Expand All @@ -514,8 +510,8 @@ define i16 @test_i16_2032_mask_shl_3(i16 %a0) {
define i16 @test_i16_2032_mask_shl_4(i16 %a0) {
; CHECK-LABEL: test_i16_2032_mask_shl_4:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0x7f0
; CHECK-NEXT: lsl w0, w8, #4
; CHECK-NEXT: lsl w8, w0, #4
; CHECK-NEXT: and w0, w8, #0x7f00
; CHECK-NEXT: ret
%t0 = and i16 %a0, 2032
%t1 = shl i16 %t0, 4
Expand All @@ -524,8 +520,8 @@ define i16 @test_i16_2032_mask_shl_4(i16 %a0) {
define i16 @test_i16_2032_mask_shl_5(i16 %a0) {
; CHECK-LABEL: test_i16_2032_mask_shl_5:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0x7f0
; CHECK-NEXT: lsl w0, w8, #5
; CHECK-NEXT: lsl w8, w0, #5
; CHECK-NEXT: and w0, w8, #0xfe00
; CHECK-NEXT: ret
%t0 = and i16 %a0, 2032
%t1 = shl i16 %t0, 5
Expand All @@ -534,8 +530,8 @@ define i16 @test_i16_2032_mask_shl_5(i16 %a0) {
define i16 @test_i16_2032_mask_shl_6(i16 %a0) {
; CHECK-LABEL: test_i16_2032_mask_shl_6:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0x3f0
; CHECK-NEXT: lsl w0, w8, #6
; CHECK-NEXT: lsl w8, w0, #6
; CHECK-NEXT: and w0, w8, #0xfc00
; CHECK-NEXT: ret
%t0 = and i16 %a0, 2032
%t1 = shl i16 %t0, 6
Expand All @@ -545,8 +541,8 @@ define i16 @test_i16_2032_mask_shl_6(i16 %a0) {
define i16 @test_i16_65024_mask_shl_1(i16 %a0) {
; CHECK-LABEL: test_i16_65024_mask_shl_1:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0x7e00
; CHECK-NEXT: lsl w0, w8, #1
; CHECK-NEXT: lsl w8, w0, #1
; CHECK-NEXT: and w0, w8, #0xfc00
; CHECK-NEXT: ret
%t0 = and i16 %a0, 65024
%t1 = shl i16 %t0, 1
Expand Down Expand Up @@ -740,8 +736,7 @@ define i32 @test_i32_4294836224_mask_ashr_18(i32 %a0) {
define i32 @test_i32_32767_mask_shl_1(i32 %a0) {
; CHECK-LABEL: test_i32_32767_mask_shl_1:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0x7fff
; CHECK-NEXT: lsl w0, w8, #1
; CHECK-NEXT: ubfiz w0, w0, #1, #15
; CHECK-NEXT: ret
%t0 = and i32 %a0, 32767
%t1 = shl i32 %t0, 1
Expand All @@ -750,8 +745,7 @@ define i32 @test_i32_32767_mask_shl_1(i32 %a0) {
define i32 @test_i32_32767_mask_shl_16(i32 %a0) {
; CHECK-LABEL: test_i32_32767_mask_shl_16:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0x7fff
; CHECK-NEXT: lsl w0, w8, #16
; CHECK-NEXT: ubfiz w0, w0, #16, #15
; CHECK-NEXT: ret
%t0 = and i32 %a0, 32767
%t1 = shl i32 %t0, 16
Expand Down Expand Up @@ -779,8 +773,8 @@ define i32 @test_i32_32767_mask_shl_18(i32 %a0) {
define i32 @test_i32_8388352_mask_shl_7(i32 %a0) {
; CHECK-LABEL: test_i32_8388352_mask_shl_7:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0x7fff00
; CHECK-NEXT: lsl w0, w8, #7
; CHECK-NEXT: lsl w8, w0, #7
; CHECK-NEXT: and w0, w8, #0x3fff8000
; CHECK-NEXT: ret
%t0 = and i32 %a0, 8388352
%t1 = shl i32 %t0, 7
Expand All @@ -789,8 +783,8 @@ define i32 @test_i32_8388352_mask_shl_7(i32 %a0) {
define i32 @test_i32_8388352_mask_shl_8(i32 %a0) {
; CHECK-LABEL: test_i32_8388352_mask_shl_8:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0x7fff00
; CHECK-NEXT: lsl w0, w8, #8
; CHECK-NEXT: lsl w8, w0, #8
; CHECK-NEXT: and w0, w8, #0x7fff0000
; CHECK-NEXT: ret
%t0 = and i32 %a0, 8388352
%t1 = shl i32 %t0, 8
Expand All @@ -799,8 +793,8 @@ define i32 @test_i32_8388352_mask_shl_8(i32 %a0) {
define i32 @test_i32_8388352_mask_shl_9(i32 %a0) {
; CHECK-LABEL: test_i32_8388352_mask_shl_9:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0x7fff00
; CHECK-NEXT: lsl w0, w8, #9
; CHECK-NEXT: lsl w8, w0, #9
; CHECK-NEXT: and w0, w8, #0xfffe0000
; CHECK-NEXT: ret
%t0 = and i32 %a0, 8388352
%t1 = shl i32 %t0, 9
Expand All @@ -809,8 +803,8 @@ define i32 @test_i32_8388352_mask_shl_9(i32 %a0) {
define i32 @test_i32_8388352_mask_shl_10(i32 %a0) {
; CHECK-LABEL: test_i32_8388352_mask_shl_10:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0x3fff00
; CHECK-NEXT: lsl w0, w8, #10
; CHECK-NEXT: lsl w8, w0, #10
; CHECK-NEXT: and w0, w8, #0xfffc0000
; CHECK-NEXT: ret
%t0 = and i32 %a0, 8388352
%t1 = shl i32 %t0, 10
Expand All @@ -820,8 +814,8 @@ define i32 @test_i32_8388352_mask_shl_10(i32 %a0) {
define i32 @test_i32_4294836224_mask_shl_1(i32 %a0) {
; CHECK-LABEL: test_i32_4294836224_mask_shl_1:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0x7ffe0000
; CHECK-NEXT: lsl w0, w8, #1
; CHECK-NEXT: lsl w8, w0, #1
; CHECK-NEXT: and w0, w8, #0xfffc0000
; CHECK-NEXT: ret
%t0 = and i32 %a0, 4294836224
%t1 = shl i32 %t0, 1
Expand Down Expand Up @@ -1015,8 +1009,7 @@ define i64 @test_i64_18446744065119617024_mask_ashr_34(i64 %a0) {
define i64 @test_i64_2147483647_mask_shl_1(i64 %a0) {
; CHECK-LABEL: test_i64_2147483647_mask_shl_1:
; CHECK: // %bb.0:
; CHECK-NEXT: and x8, x0, #0x7fffffff
; CHECK-NEXT: lsl x0, x8, #1
; CHECK-NEXT: lsl w0, w0, #1
; CHECK-NEXT: ret
%t0 = and i64 %a0, 2147483647
%t1 = shl i64 %t0, 1
Expand Down Expand Up @@ -1054,8 +1047,8 @@ define i64 @test_i64_2147483647_mask_shl_34(i64 %a0) {
define i64 @test_i64_140737488289792_mask_shl_15(i64 %a0) {
; CHECK-LABEL: test_i64_140737488289792_mask_shl_15:
; CHECK: // %bb.0:
; CHECK-NEXT: and x8, x0, #0x7fffffff0000
; CHECK-NEXT: lsl x0, x8, #15
; CHECK-NEXT: lsl x8, x0, #15
; CHECK-NEXT: and x0, x8, #0x3fffffff80000000
; CHECK-NEXT: ret
%t0 = and i64 %a0, 140737488289792
%t1 = shl i64 %t0, 15
Expand All @@ -1064,8 +1057,8 @@ define i64 @test_i64_140737488289792_mask_shl_15(i64 %a0) {
define i64 @test_i64_140737488289792_mask_shl_16(i64 %a0) {
; CHECK-LABEL: test_i64_140737488289792_mask_shl_16:
; CHECK: // %bb.0:
; CHECK-NEXT: and x8, x0, #0x7fffffff0000
; CHECK-NEXT: lsl x0, x8, #16
; CHECK-NEXT: lsl x8, x0, #16
; CHECK-NEXT: and x0, x8, #0x7fffffff00000000
; CHECK-NEXT: ret
%t0 = and i64 %a0, 140737488289792
%t1 = shl i64 %t0, 16
Expand All @@ -1074,8 +1067,8 @@ define i64 @test_i64_140737488289792_mask_shl_16(i64 %a0) {
define i64 @test_i64_140737488289792_mask_shl_17(i64 %a0) {
; CHECK-LABEL: test_i64_140737488289792_mask_shl_17:
; CHECK: // %bb.0:
; CHECK-NEXT: and x8, x0, #0x7fffffff0000
; CHECK-NEXT: lsl x0, x8, #17
; CHECK-NEXT: lsl x8, x0, #17
; CHECK-NEXT: and x0, x8, #0xfffffffe00000000
; CHECK-NEXT: ret
%t0 = and i64 %a0, 140737488289792
%t1 = shl i64 %t0, 17
Expand All @@ -1084,8 +1077,8 @@ define i64 @test_i64_140737488289792_mask_shl_17(i64 %a0) {
define i64 @test_i64_140737488289792_mask_shl_18(i64 %a0) {
; CHECK-LABEL: test_i64_140737488289792_mask_shl_18:
; CHECK: // %bb.0:
; CHECK-NEXT: and x8, x0, #0x3fffffff0000
; CHECK-NEXT: lsl x0, x8, #18
; CHECK-NEXT: lsl x8, x0, #18
; CHECK-NEXT: and x0, x8, #0xfffffffc00000000
; CHECK-NEXT: ret
%t0 = and i64 %a0, 140737488289792
%t1 = shl i64 %t0, 18
Expand All @@ -1095,8 +1088,8 @@ define i64 @test_i64_140737488289792_mask_shl_18(i64 %a0) {
define i64 @test_i64_18446744065119617024_mask_shl_1(i64 %a0) {
; CHECK-LABEL: test_i64_18446744065119617024_mask_shl_1:
; CHECK: // %bb.0:
; CHECK-NEXT: and x8, x0, #0x7ffffffe00000000
; CHECK-NEXT: lsl x0, x8, #1
; CHECK-NEXT: lsl x8, x0, #1
; CHECK-NEXT: and x0, x8, #0xfffffffc00000000
; CHECK-NEXT: ret
%t0 = and i64 %a0, 18446744065119617024
%t1 = shl i64 %t0, 1
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/AArch64/extract-bits.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1013,8 +1013,8 @@ define i32 @c1_i32(i32 %arg) nounwind {
define i32 @c2_i32(i32 %arg) nounwind {
; CHECK-LABEL: c2_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ubfx w8, w0, #19, #10
; CHECK-NEXT: lsl w0, w8, #2
; CHECK-NEXT: lsr w8, w0, #17
; CHECK-NEXT: and w0, w8, #0xffc
; CHECK-NEXT: ret
%tmp0 = lshr i32 %arg, 19
%tmp1 = and i32 %tmp0, 1023
Expand Down Expand Up @@ -1063,8 +1063,8 @@ define i64 @c1_i64(i64 %arg) nounwind {
define i64 @c2_i64(i64 %arg) nounwind {
; CHECK-LABEL: c2_i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ubfx x8, x0, #51, #10
; CHECK-NEXT: lsl x0, x8, #2
; CHECK-NEXT: lsr x8, x0, #49
; CHECK-NEXT: and x0, x8, #0xffc
; CHECK-NEXT: ret
%tmp0 = lshr i64 %arg, 51
%tmp1 = and i64 %tmp0, 1023
Expand Down Expand Up @@ -1120,8 +1120,8 @@ define void @c6_i32(i32 %arg, ptr %ptr) nounwind {
define void @c7_i32(i32 %arg, ptr %ptr) nounwind {
; CHECK-LABEL: c7_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ubfx w8, w0, #19, #10
; CHECK-NEXT: lsl w8, w8, #2
; CHECK-NEXT: lsr w8, w0, #17
; CHECK-NEXT: and w8, w8, #0xffc
; CHECK-NEXT: str w8, [x1]
; CHECK-NEXT: ret
%tmp0 = lshr i32 %arg, 19
Expand Down Expand Up @@ -1163,8 +1163,8 @@ define void @c6_i64(i64 %arg, ptr %ptr) nounwind {
define void @c7_i64(i64 %arg, ptr %ptr) nounwind {
; CHECK-LABEL: c7_i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ubfx x8, x0, #51, #10
; CHECK-NEXT: lsl x8, x8, #2
; CHECK-NEXT: lsr x8, x0, #49
; CHECK-NEXT: and x8, x8, #0xffc
; CHECK-NEXT: str x8, [x1]
; CHECK-NEXT: ret
%tmp0 = lshr i64 %arg, 51
Expand Down
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