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[X86][MC] Fix offset for R_X86_64_CODE_6_GOTTPOFF fixup #119496

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Merged
merged 1 commit into from
Dec 13, 2024
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[X86][MC] Fix offset for R_X86_64_CODE_6_GOTTPOFF fixup #119496

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18 changes: 9 additions & 9 deletions lld/test/ELF/tls-opt.s
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Original file line number Diff line number Diff line change
Expand Up @@ -28,17 +28,17 @@
// DISASM-NEXT: addq $-8, %r28
// DISASM-NEXT: addq $-4, %r16
# NDD
// DISASM-NEXT: addq $-10, %r16, %r16
// DISASM-NEXT: addq $-10, %r16, %r20
// DISASM-NEXT: addq $-10, %r16, %rax
// DISASM-NEXT: addq $-10, %rax, %r16
// DISASM-NEXT: addq $-10, %r8, %r16
// DISASM-NEXT: addq $-10, %rax, %r12
// DISASM-NEXT: addq $-8, %r16, %r16
// DISASM-NEXT: addq $-8, %r16, %r20
// DISASM-NEXT: addq $-8, %r16, %rax
// DISASM-NEXT: addq $-8, %rax, %r16
// DISASM-NEXT: addq $-8, %r8, %r16
// DISASM-NEXT: addq $-8, %rax, %r12
# NDD + NF
// DISASM-NEXT: {nf} addq $-10, %r8, %r16
// DISASM-NEXT: {nf} addq $-10, %rax, %r12
// DISASM-NEXT: {nf} addq $-8, %r8, %r16
// DISASM-NEXT: {nf} addq $-8, %rax, %r12
# NF
// DISASM-NEXT: {nf} addq $-10, %r12
// DISASM-NEXT: {nf} addq $-8, %r12

// LD to LE:
// DISASM-NEXT: movq %fs:0, %rax
Expand Down
20 changes: 10 additions & 10 deletions lld/test/ELF/x86-64-tls-ie-local.s
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Expand Up @@ -17,21 +17,21 @@
## &.got[1] - 0x1286 = 0x2380 - 0x1286 = 4346
## &.got[2] - 0x128e = 0x2378 - 0x128e = 4330
## &.got[3] - 0x1296 = 0x2380 - 0x1296 = 4330
## &.got[0] - 0x12a0 = 0x2376 - 0x12a0 = 4310
## &.got[1] - 0x12aa = 0x237e - 0x12aa = 4308
## &.got[0] - 0x12b4 = 0x2376 - 0x12b4 = 4290
## &.got[1] - 0x12be = 0x237e - 0x12be = 4288
## &.got[0] - 0x12c8 = 0x2376 - 0x12c8 = 4270
## &.got[0] - 0x12a0 = 0x2378 - 0x12a0 = 4312
## &.got[1] - 0x12aa = 0x2380 - 0x12aa = 4310
## &.got[0] - 0x12b4 = 0x2378 - 0x12b4 = 4292
## &.got[1] - 0x12be = 0x2380 - 0x12be = 4290
## &.got[0] - 0x12c8 = 0x2378 - 0x12c8 = 4272

# CHECK: 1278: addq 4345(%rip), %rax
# CHECK-NEXT: 127f: addq 4346(%rip), %rax
# CHECK-NEXT: 1286: addq 4330(%rip), %r16
# CHECK-NEXT: 128e: addq 4330(%rip), %r16
# CHECK-NEXT: 1296: addq %r8, 4310(%rip), %r16
# CHECK-NEXT: 12a0: addq 4308(%rip), %rax, %r12
# CHECK-NEXT: 12aa: {nf} addq %r8, 4290(%rip), %r16
# CHECK-NEXT: 12b4: {nf} addq 4288(%rip), %rax, %r12
# CHECK-NEXT: 12be: {nf} addq 4270(%rip), %r12
# CHECK-NEXT: 1296: addq %r8, 4312(%rip), %r16
# CHECK-NEXT: 12a0: addq 4310(%rip), %rax, %r12
# CHECK-NEXT: 12aa: {nf} addq %r8, 4292(%rip), %r16
# CHECK-NEXT: 12b4: {nf} addq 4290(%rip), %rax, %r12
# CHECK-NEXT: 12be: {nf} addq 4272(%rip), %r12

addq foo@GOTTPOFF(%rip), %rax
addq bar@GOTTPOFF(%rip), %rax
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
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Expand Up @@ -634,7 +634,7 @@ const MCFixupKindInfo &X86AsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
{"reloc_riprel_4byte_relax", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
{"reloc_riprel_4byte_relax_rex", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
{"reloc_riprel_4byte_relax_rex2", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
{"reloc_riprel_6byte_relax", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
{"reloc_riprel_4byte_relax_evex", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
{"reloc_signed_4byte", 0, 32, 0},
{"reloc_signed_4byte_relax", 0, 32, 0},
{"reloc_global_offset_table", 0, 32, 0},
Expand Down Expand Up @@ -684,7 +684,7 @@ static unsigned getFixupKindSize(unsigned Kind) {
case X86::reloc_riprel_4byte_relax_rex2:
case X86::reloc_riprel_4byte_movq_load:
case X86::reloc_riprel_4byte_movq_load_rex2:
case X86::reloc_riprel_6byte_relax:
case X86::reloc_riprel_4byte_relax_evex:
case X86::reloc_signed_4byte:
case X86::reloc_signed_4byte_relax:
case X86::reloc_global_offset_table:
Expand Down
6 changes: 2 additions & 4 deletions llvm/lib/Target/X86/MCTargetDesc/X86ELFObjectWriter.cpp
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Expand Up @@ -77,7 +77,7 @@ static X86_64RelType getType64(MCFixupKind Kind,
case X86::reloc_riprel_4byte_relax_rex2:
case X86::reloc_riprel_4byte_movq_load:
case X86::reloc_riprel_4byte_movq_load_rex2:
case X86::reloc_riprel_6byte_relax:
case X86::reloc_riprel_4byte_relax_evex:
return RT64_32;
case X86::reloc_branch_4byte_pcrel:
Modifier = MCSymbolRefExpr::VK_PLT;
Expand Down Expand Up @@ -203,7 +203,7 @@ static unsigned getRelocType64(MCContext &Ctx, SMLoc Loc,
if ((unsigned)Kind == X86::reloc_riprel_4byte_movq_load_rex2 ||
(unsigned)Kind == X86::reloc_riprel_4byte_relax_rex2)
return ELF::R_X86_64_CODE_4_GOTTPOFF;
else if ((unsigned)Kind == X86::reloc_riprel_6byte_relax)
else if ((unsigned)Kind == X86::reloc_riprel_4byte_relax_evex)
return ELF::R_X86_64_CODE_6_GOTTPOFF;
return ELF::R_X86_64_GOTTPOFF;
case MCSymbolRefExpr::VK_TLSLD:
Expand All @@ -230,8 +230,6 @@ static unsigned getRelocType64(MCContext &Ctx, SMLoc Loc,
case X86::reloc_riprel_4byte_relax_rex2:
case X86::reloc_riprel_4byte_movq_load_rex2:
return ELF::R_X86_64_CODE_4_GOTPCRELX;
case X86::reloc_riprel_6byte_relax:
return ELF::R_X86_64_CODE_6_GOTTPOFF;
}
llvm_unreachable("unexpected relocation type!");
case MCSymbolRefExpr::VK_GOTPCREL_NORELAX:
Expand Down
5 changes: 3 additions & 2 deletions llvm/lib/Target/X86/MCTargetDesc/X86FixupKinds.h
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Expand Up @@ -24,8 +24,9 @@ enum Fixups {
// instruction with rex prefix
reloc_riprel_4byte_relax_rex2, // 32-bit rip-relative in relaxable
// instruction with rex2 prefix
reloc_riprel_6byte_relax, // 32-bit rip-relative in relaxable
// instruction with APX NDD
reloc_riprel_4byte_relax_evex, // 32-bit rip-relative in relaxable
// instruction of APX NDD/NF with
// EVEX prefix
reloc_signed_4byte, // 32-bit signed. Unlike FK_Data_4
// this will be sign extended at
// runtime.
Expand Down
8 changes: 4 additions & 4 deletions llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
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Expand Up @@ -572,15 +572,15 @@ void X86MCCodeEmitter::emitImmediate(const MCOperand &DispOp, SMLoc Loc,
FixupKind == MCFixupKind(X86::reloc_riprel_4byte_relax) ||
FixupKind == MCFixupKind(X86::reloc_riprel_4byte_relax_rex) ||
FixupKind == MCFixupKind(X86::reloc_riprel_4byte_relax_rex2) ||
FixupKind == MCFixupKind(X86::reloc_branch_4byte_pcrel)) {
FixupKind == MCFixupKind(X86::reloc_branch_4byte_pcrel) ||
FixupKind == MCFixupKind(X86::reloc_riprel_4byte_relax_evex)) {
ImmOffset -= 4;
// If this is a pc-relative load off _GLOBAL_OFFSET_TABLE_:
// leaq _GLOBAL_OFFSET_TABLE_(%rip), %r15
// this needs to be a GOTPC32 relocation.
if (startsWithGlobalOffsetTable(Expr) != GOT_None)
FixupKind = MCFixupKind(X86::reloc_global_offset_table);
} else if (FixupKind == MCFixupKind(X86::reloc_riprel_6byte_relax))
ImmOffset -= 6;
}

if (FixupKind == FK_PCRel_2)
ImmOffset -= 2;
Expand Down Expand Up @@ -677,7 +677,7 @@ void X86MCCodeEmitter::emitMemModRMByte(
case X86::ADD64mr_ND:
case X86::ADD64mr_NF_ND:
case X86::ADD64rm_NF_ND:
return X86::reloc_riprel_6byte_relax;
return X86::reloc_riprel_4byte_relax_evex;
}
}();

Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/X86/MCTargetDesc/X86MachObjectWriter.cpp
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Expand Up @@ -70,7 +70,7 @@ static bool isFixupKindRIPRel(unsigned Kind) {
Kind == X86::reloc_riprel_4byte_relax ||
Kind == X86::reloc_riprel_4byte_relax_rex ||
Kind == X86::reloc_riprel_4byte_relax_rex2 ||
Kind == X86::reloc_riprel_6byte_relax;
Kind == X86::reloc_riprel_4byte_relax_evex;
}

static unsigned getFixupKindLog2Size(unsigned Kind) {
Expand All @@ -92,7 +92,7 @@ static unsigned getFixupKindLog2Size(unsigned Kind) {
case X86::reloc_signed_4byte:
case X86::reloc_signed_4byte_relax:
case X86::reloc_branch_4byte_pcrel:
case X86::reloc_riprel_6byte_relax:
case X86::reloc_riprel_4byte_relax_evex:
case FK_Data_4: return 2;
case FK_Data_8: return 3;
}
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/X86/MCTargetDesc/X86WinCOFFObjectWriter.cpp
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Expand Up @@ -70,7 +70,7 @@ unsigned X86WinCOFFObjectWriter::getRelocType(MCContext &Ctx,
case X86::reloc_riprel_4byte_relax:
case X86::reloc_riprel_4byte_relax_rex:
case X86::reloc_riprel_4byte_relax_rex2:
case X86::reloc_riprel_6byte_relax:
case X86::reloc_riprel_4byte_relax_evex:
case X86::reloc_branch_4byte_pcrel:
return COFF::IMAGE_REL_AMD64_REL32;
case FK_Data_4:
Expand Down
10 changes: 5 additions & 5 deletions llvm/test/MC/ELF/relocation.s
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Expand Up @@ -90,11 +90,11 @@ weak_sym:
// CHECK-NEXT: 0x2D R_X86_64_GOTTPOFF foo 0xFFFFFFFFFFFFFFFC
// CHECK-NEXT: 0x35 R_X86_64_CODE_4_GOTTPOFF foo 0xFFFFFFFFFFFFFFFC
// CHECK-NEXT: 0x3D R_X86_64_CODE_4_GOTTPOFF foo 0xFFFFFFFFFFFFFFFC
// CHECK-NEXT: 0x47 R_X86_64_CODE_6_GOTTPOFF foo 0xFFFFFFFFFFFFFFFA
// CHECK-NEXT: 0x51 R_X86_64_CODE_6_GOTTPOFF foo 0xFFFFFFFFFFFFFFFA
// CHECK-NEXT: 0x5B R_X86_64_CODE_6_GOTTPOFF foo 0xFFFFFFFFFFFFFFFA
// CHECK-NEXT: 0x65 R_X86_64_CODE_6_GOTTPOFF foo 0xFFFFFFFFFFFFFFFA
// CHECK-NEXT: 0x6F R_X86_64_CODE_6_GOTTPOFF foo 0xFFFFFFFFFFFFFFFA
// CHECK-NEXT: 0x47 R_X86_64_CODE_6_GOTTPOFF foo 0xFFFFFFFFFFFFFFFC
// CHECK-NEXT: 0x51 R_X86_64_CODE_6_GOTTPOFF foo 0xFFFFFFFFFFFFFFFC
// CHECK-NEXT: 0x5B R_X86_64_CODE_6_GOTTPOFF foo 0xFFFFFFFFFFFFFFFC
// CHECK-NEXT: 0x65 R_X86_64_CODE_6_GOTTPOFF foo 0xFFFFFFFFFFFFFFFC
// CHECK-NEXT: 0x6F R_X86_64_CODE_6_GOTTPOFF foo 0xFFFFFFFFFFFFFFFC
// CHECK-NEXT: 0x76 R_X86_64_TLSGD foo 0xFFFFFFFFFFFFFFFC
// CHECK-NEXT: 0x7D R_X86_64_TPOFF32 foo 0x0
// CHECK-NEXT: 0x84 R_X86_64_TLSLD foo 0xFFFFFFFFFFFFFFFC
Expand Down
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