Skip to content

[GlobalISel] Use replaceRegOrBuildCopy when legalizer-combining anyext(undef). #119721

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom
Merged
merged 1 commit into from
Dec 13, 2024
Merged

[GlobalISel] Use replaceRegOrBuildCopy when legalizer-combining anyext(undef). #119721

merged 1 commit into from
Dec 13, 2024

Conversation

davemgreen
Copy link
Collaborator

This just avoids the unnecessary creation of some COPY nodes created from the CSE builder.

@llvmbot
Copy link
Member

llvmbot commented Dec 12, 2024

@llvm/pr-subscribers-backend-aarch64

Author: David Green (davemgreen)

Changes

This just avoids the unnecessary creation of some COPY nodes created from the CSE builder.

Patch is 27.65 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/119721.diff

5 Files Affected:

  • (modified) llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h (+8-5)
  • (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-ext-debugloc.mir (+1-1)
  • (modified) llvm/test/CodeGen/AArch64/GlobalISel/legalize-build-vector.mir (+1-2)
  • (modified) llvm/test/CodeGen/AArch64/GlobalISel/legalize-concat-vectors.mir (+2-6)
  • (modified) llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir (+62-124)
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h b/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
index 9dea4c1b412dbb..3580ec0f0f4c37 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
@@ -112,7 +112,7 @@ class LegalizationArtifactCombiner {
         return true;
       }
     }
-    return tryFoldImplicitDef(MI, DeadInsts, UpdatedDefs);
+    return tryFoldImplicitDef(MI, DeadInsts, UpdatedDefs, Observer);
   }
 
   bool tryCombineZExt(MachineInstr &MI,
@@ -187,7 +187,7 @@ class LegalizationArtifactCombiner {
         return true;
       }
     }
-    return tryFoldImplicitDef(MI, DeadInsts, UpdatedDefs);
+    return tryFoldImplicitDef(MI, DeadInsts, UpdatedDefs, Observer);
   }
 
   bool tryCombineSExt(MachineInstr &MI,
@@ -252,7 +252,7 @@ class LegalizationArtifactCombiner {
       }
     }
 
-    return tryFoldImplicitDef(MI, DeadInsts, UpdatedDefs);
+    return tryFoldImplicitDef(MI, DeadInsts, UpdatedDefs, Observer);
   }
 
   bool tryCombineTrunc(MachineInstr &MI,
@@ -376,7 +376,8 @@ class LegalizationArtifactCombiner {
   /// Try to fold G_[ASZ]EXT (G_IMPLICIT_DEF).
   bool tryFoldImplicitDef(MachineInstr &MI,
                           SmallVectorImpl<MachineInstr *> &DeadInsts,
-                          SmallVectorImpl<Register> &UpdatedDefs) {
+                          SmallVectorImpl<Register> &UpdatedDefs,
+                          GISelObserverWrapper &Observer) {
     unsigned Opcode = MI.getOpcode();
     assert(Opcode == TargetOpcode::G_ANYEXT || Opcode == TargetOpcode::G_ZEXT ||
            Opcode == TargetOpcode::G_SEXT);
@@ -392,7 +393,9 @@ class LegalizationArtifactCombiner {
         if (!isInstLegal({TargetOpcode::G_IMPLICIT_DEF, {DstTy}}))
           return false;
         LLVM_DEBUG(dbgs() << ".. Combine G_ANYEXT(G_IMPLICIT_DEF): " << MI;);
-        Builder.buildInstr(TargetOpcode::G_IMPLICIT_DEF, {DstReg}, {});
+        auto Impl = Builder.buildInstr(TargetOpcode::G_IMPLICIT_DEF, {DstTy}, {});
+        replaceRegOrBuildCopy(DstReg, Impl.getReg(0), MRI, Builder, UpdatedDefs,
+                              Observer);
         UpdatedDefs.push_back(DstReg);
       } else {
         // G_[SZ]EXT (G_IMPLICIT_DEF) -> G_CONSTANT 0 because the top
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-ext-debugloc.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-ext-debugloc.mir
index 7296e10b4a61e3..e16faa6ba9e6b8 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-ext-debugloc.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-ext-debugloc.mir
@@ -2,7 +2,7 @@
 
 # Check that when we combine ZEXT/ANYEXT we assign the correct location.
 # CHECK: !8 = !DILocation(line: 23, column: 5, scope: !4)
-# CHECK:  G_AND %14, %15, debug-location !8
+# CHECK:  G_AND %16, %15, debug-location !8
 
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-build-vector.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-build-vector.mir
index a63d8b9c137725..6b9b08e2f9f4d6 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-build-vector.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-build-vector.mir
@@ -141,8 +141,7 @@ body: |
   bb.0:
     ; CHECK-LABEL: name: widen_v2s8
     ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[DEF]](s32)
+    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[DEF]](s32), [[DEF]](s32)
     ; CHECK-NEXT: $d0 = COPY [[BUILD_VECTOR]](<2 x s32>)
     ; CHECK-NEXT: RET_ReallyLR
     %0:_(s8) = G_IMPLICIT_DEF
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-concat-vectors.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-concat-vectors.mir
index 87bbbee35d6d62..5527cbfb682b42 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-concat-vectors.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-concat-vectors.mir
@@ -75,10 +75,7 @@ body:             |
     ; CHECK-NEXT: %b:_(s32) = G_LOAD %a(p0) :: (load (s32))
     ; CHECK-NEXT: %c:_(<4 x s8>) = G_BITCAST %b(s32)
     ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY [[DEF]](s16)
-    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY [[DEF]](s16)
-    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s16) = COPY [[DEF]](s16)
-    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[COPY]](s16), [[COPY1]](s16), [[COPY2]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16)
+    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16)
     ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[BUILD_VECTOR]](<8 x s16>)
     ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s8>), [[UV1:%[0-9]+]]:_(<4 x s8>) = G_UNMERGE_VALUES [[TRUNC]](<8 x s8>)
     ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST %c(<4 x s8>)
@@ -113,8 +110,7 @@ body:             |
     ; CHECK-NEXT: %b:_(s32) = G_LOAD %a(p0) :: (load (s32))
     ; CHECK-NEXT: %c:_(<2 x s16>) = G_BITCAST %b(s32)
     ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32)
+    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32)
     ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[BUILD_VECTOR]](<4 x s32>)
     ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[TRUNC]](<4 x s16>)
     ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST %c(<2 x s16>)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
index 942bb60f5c0623..eb9c3ff60c7045 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
@@ -67,258 +67,196 @@ body: |
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x2
     ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
-    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
     ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C1]](s64)
     ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
     ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
     ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL]]
-    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
     ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C2]](s64)
     ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
-    ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+    ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
     ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C3]](s64)
     ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
-    ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
+    ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
     ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C4]](s64)
     ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[SHL3]]
-    ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
+    ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
     ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C5]](s64)
     ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
-    ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C]]
+    ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
     ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C6]](s64)
     ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
-    ; CHECK-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C]]
+    ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
     ; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C7]](s64)
     ; CHECK-NEXT: [[OR6:%[0-9]+]]:_(s32) = G_OR [[OR5]], [[SHL6]]
     ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[OR6]](s32)
-    ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C]]
+    ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C1]](s64)
-    ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
+    ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[OR7:%[0-9]+]]:_(s32) = G_OR [[AND9]], [[SHL7]]
-    ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]
+    ; CHECK-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C2]](s64)
     ; CHECK-NEXT: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
-    ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C]]
+    ; CHECK-NEXT: [[AND11:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C3]](s64)
     ; CHECK-NEXT: [[OR9:%[0-9]+]]:_(s32) = G_OR [[OR8]], [[SHL9]]
-    ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C]]
+    ; CHECK-NEXT: [[AND12:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND12]], [[C4]](s64)
     ; CHECK-NEXT: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
-    ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C]]
+    ; CHECK-NEXT: [[AND13:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C5]](s64)
     ; CHECK-NEXT: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
-    ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C]]
+    ; CHECK-NEXT: [[AND14:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C6]](s64)
     ; CHECK-NEXT: [[OR12:%[0-9]+]]:_(s32) = G_OR [[OR11]], [[SHL12]]
-    ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C]]
+    ; CHECK-NEXT: [[AND15:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C7]](s64)
     ; CHECK-NEXT: [[OR13:%[0-9]+]]:_(s32) = G_OR [[OR12]], [[SHL13]]
     ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[OR13]](s32)
-    ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C]]
+    ; CHECK-NEXT: [[AND16:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND16]], [[C1]](s64)
-    ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C]]
+    ; CHECK-NEXT: [[AND17:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[OR14:%[0-9]+]]:_(s32) = G_OR [[AND17]], [[SHL14]]
-    ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C]]
+    ; CHECK-NEXT: [[AND18:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND18]], [[C2]](s64)
     ; CHECK-NEXT: [[OR15:%[0-9]+]]:_(s32) = G_OR [[OR14]], [[SHL15]]
-    ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C]]
+    ; CHECK-NEXT: [[AND19:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL16:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[C3]](s64)
     ; CHECK-NEXT: [[OR16:%[0-9]+]]:_(s32) = G_OR [[OR15]], [[SHL16]]
-    ; CHECK-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND20:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C]]
+    ; CHECK-NEXT: [[AND20:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL17:%[0-9]+]]:_(s32) = G_SHL [[AND20]], [[C4]](s64)
     ; CHECK-NEXT: [[OR17:%[0-9]+]]:_(s32) = G_OR [[OR16]], [[SHL17]]
-    ; CHECK-NEXT: [[COPY22:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C]]
+    ; CHECK-NEXT: [[AND21:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL18:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[C5]](s64)
     ; CHECK-NEXT: [[OR18:%[0-9]+]]:_(s32) = G_OR [[OR17]], [[SHL18]]
-    ; CHECK-NEXT: [[COPY23:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C]]
+    ; CHECK-NEXT: [[AND22:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL19:%[0-9]+]]:_(s32) = G_SHL [[AND22]], [[C6]](s64)
     ; CHECK-NEXT: [[OR19:%[0-9]+]]:_(s32) = G_OR [[OR18]], [[SHL19]]
-    ; CHECK-NEXT: [[COPY24:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C]]
+    ; CHECK-NEXT: [[AND23:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL20:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[C7]](s64)
     ; CHECK-NEXT: [[OR20:%[0-9]+]]:_(s32) = G_OR [[OR19]], [[SHL20]]
     ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[OR20]](s32)
-    ; CHECK-NEXT: [[COPY25:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND24:%[0-9]+]]:_(s32) = G_AND [[COPY25]], [[C]]
+    ; CHECK-NEXT: [[AND24:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL21:%[0-9]+]]:_(s32) = G_SHL [[AND24]], [[C1]](s64)
-    ; CHECK-NEXT: [[COPY26:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND25:%[0-9]+]]:_(s32) = G_AND [[COPY26]], [[C]]
+    ; CHECK-NEXT: [[AND25:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[OR21:%[0-9]+]]:_(s32) = G_OR [[AND25]], [[SHL21]]
-    ; CHECK-NEXT: [[COPY27:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND26:%[0-9]+]]:_(s32) = G_AND [[COPY27]], [[C]]
+    ; CHECK-NEXT: [[AND26:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL22:%[0-9]+]]:_(s32) = G_SHL [[AND26]], [[C2]](s64)
     ; CHECK-NEXT: [[OR22:%[0-9]+]]:_(s32) = G_OR [[OR21]], [[SHL22]]
-    ; CHECK-NEXT: [[COPY28:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND27:%[0-9]+]]:_(s32) = G_AND [[COPY28]], [[C]]
+    ; CHECK-NEXT: [[AND27:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL23:%[0-9]+]]:_(s32) = G_SHL [[AND27]], [[C3]](s64)
     ; CHECK-NEXT: [[OR23:%[0-9]+]]:_(s32) = G_OR [[OR22]], [[SHL23]]
-    ; CHECK-NEXT: [[COPY29:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND28:%[0-9]+]]:_(s32) = G_AND [[COPY29]], [[C]]
+    ; CHECK-NEXT: [[AND28:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL24:%[0-9]+]]:_(s32) = G_SHL [[AND28]], [[C4]](s64)
     ; CHECK-NEXT: [[OR24:%[0-9]+]]:_(s32) = G_OR [[OR23]], [[SHL24]]
-    ; CHECK-NEXT: [[COPY30:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND29:%[0-9]+]]:_(s32) = G_AND [[COPY30]], [[C]]
+    ; CHECK-NEXT: [[AND29:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL25:%[0-9]+]]:_(s32) = G_SHL [[AND29]], [[C5]](s64)
     ; CHECK-NEXT: [[OR25:%[0-9]+]]:_(s32) = G_OR [[OR24]], [[SHL25]]
-    ; CHECK-NEXT: [[COPY31:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND30:%[0-9]+]]:_(s32) = G_AND [[COPY31]], [[C]]
+    ; CHECK-NEXT: [[AND30:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL26:%[0-9]+]]:_(s32) = G_SHL [[AND30]], [[C6]](s64)
     ; CHECK-NEXT: [[OR26:%[0-9]+]]:_(s32) = G_OR [[OR25]], [[SHL26]]
-    ; CHECK-NEXT: [[COPY32:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND31:%[0-9]+]]:_(s32) = G_AND [[COPY32]], [[C]]
+    ; CHECK-NEXT: [[AND31:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL27:%[0-9]+]]:_(s32) = G_SHL [[AND31]], [[C7]](s64)
     ; CHECK-NEXT: [[OR27:%[0-9]+]]:_(s32) = G_OR [[OR26]], [[SHL27]]
     ; CHECK-NEXT: [[TRUNC4:%[0-9]+]]:_(s8) = G_TRUNC [[OR27]](s32)
-    ; CHECK-NEXT: [[COPY33:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND32:%[0-9]+]]:_(s32) = G_AND [[COPY33]], [[C]]
+    ; CHECK-NEXT: [[AND32:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL28:%[0-9]+]]:_(s32) = G_SHL [[AND32]], [[C1]](s64)
-    ; CHECK-NEXT: [[COPY34:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND33:%[0-9]+]]:_(s32) = G_AND [[COPY34]], [[C]]
+    ; CHECK-NEXT: [[AND33:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[OR28:%[0-9]+]]:_(s32) = G_OR [[AND33]], [[SHL28]]
-    ; CHECK-NEXT: [[COPY35:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND34:%[0-9]+]]:_(s32) = G_AND [[COPY35]], [[C]]
+    ; CHECK-NEXT: [[AND34:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL29:%[0-9]+]]:_(s32) = G_SHL [[AND34]], [[C2]](s64)
     ; CHECK-NEXT: [[OR29:%[0-9]+]]:_(s32) = G_OR [[OR28]], [[SHL29]]
-    ; CHECK-NEXT: [[COPY36:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND35:%[0-9]+]]:_(s32) = G_AND [[COPY36]], [[C]]
+    ; CHECK-NEXT: [[AND35:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL30:%[0-9]+]]:_(s32) = G_SHL [[AND35]], [[C3]](s64)
     ; CHECK-NEXT: [[OR30:%[0-9]+]]:_(s32) = G_OR [[OR29]], [[SHL30]]
-    ; CHECK-NEXT: [[COPY37:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND36:%[0-9]+]]:_(s32) = G_AND [[COPY37]], [[C]]
+    ; CHECK-NEXT: [[AND36:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL31:%[0-9]+]]:_(s32) = G_SHL [[AND36]], [[C4]](s64)
     ; CHECK-NEXT: [[OR31:%[0-9]+]]:_(s32) = G_OR [[OR30]], [[SHL31]]
-    ; CHECK-NEXT: [[COPY38:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND37:%[0-9]+]]:_(s32) = G_AND [[COPY38]], [[C]]
+    ; CHECK-NEXT: [[AND37:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL32:%[0-9]+]]:_(s32) = G_SHL [[AND37]], [[C5]](s64)
     ; CHECK-NEXT: [[OR32:%[0-9]+]]:_(s32) = G_OR [[OR31]], [[SHL32]]
-    ; CHECK-NEXT: [[COPY39:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND38:%[0-9]+]]:_(s32) = G_AND [[COPY39]], [[C]]
+    ; CHECK-NEXT: [[AND38:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL33:%[0-9]+]]:_(s32) = G_SHL [[AND38]], [[C6]](s64)
     ; CHECK-NEXT: [[OR33:%[0-9]+]]:_(s32) = G_OR [[OR32]], [[SHL33]]
-    ; CHECK-NEXT: [[COPY40:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND39:%[0-9]+]]:_(s32) = G_AND [[COPY40]], [[C]]
+    ; CHECK-NEXT: [[AND39:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL34:%[0-9]+]]:_(s32) = G_SHL [[AND39]], [[C7]](s64)
     ; CHECK-NEXT: [[OR34:%[0-9]+]]:_(s32) = G_OR [[OR33]], [[SHL34]]
     ; CHECK-NEXT: [[TRUNC5:%[0-9]+]]:_(s8) = G_TRUNC [[OR34]](s32)
-    ; CHECK-NEXT: [[COPY41:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND40:%[0-9]+]]:_(s32) = G_AND [[COPY41]], [...
[truncated]

@llvmbot
Copy link
Member

llvmbot commented Dec 12, 2024

@llvm/pr-subscribers-llvm-globalisel

Author: David Green (davemgreen)

Changes

This just avoids the unnecessary creation of some COPY nodes created from the CSE builder.

Patch is 27.65 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/119721.diff

5 Files Affected:

  • (modified) llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h (+8-5)
  • (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-ext-debugloc.mir (+1-1)
  • (modified) llvm/test/CodeGen/AArch64/GlobalISel/legalize-build-vector.mir (+1-2)
  • (modified) llvm/test/CodeGen/AArch64/GlobalISel/legalize-concat-vectors.mir (+2-6)
  • (modified) llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir (+62-124)
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h b/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
index 9dea4c1b412dbb..3580ec0f0f4c37 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
@@ -112,7 +112,7 @@ class LegalizationArtifactCombiner {
         return true;
       }
     }
-    return tryFoldImplicitDef(MI, DeadInsts, UpdatedDefs);
+    return tryFoldImplicitDef(MI, DeadInsts, UpdatedDefs, Observer);
   }
 
   bool tryCombineZExt(MachineInstr &MI,
@@ -187,7 +187,7 @@ class LegalizationArtifactCombiner {
         return true;
       }
     }
-    return tryFoldImplicitDef(MI, DeadInsts, UpdatedDefs);
+    return tryFoldImplicitDef(MI, DeadInsts, UpdatedDefs, Observer);
   }
 
   bool tryCombineSExt(MachineInstr &MI,
@@ -252,7 +252,7 @@ class LegalizationArtifactCombiner {
       }
     }
 
-    return tryFoldImplicitDef(MI, DeadInsts, UpdatedDefs);
+    return tryFoldImplicitDef(MI, DeadInsts, UpdatedDefs, Observer);
   }
 
   bool tryCombineTrunc(MachineInstr &MI,
@@ -376,7 +376,8 @@ class LegalizationArtifactCombiner {
   /// Try to fold G_[ASZ]EXT (G_IMPLICIT_DEF).
   bool tryFoldImplicitDef(MachineInstr &MI,
                           SmallVectorImpl<MachineInstr *> &DeadInsts,
-                          SmallVectorImpl<Register> &UpdatedDefs) {
+                          SmallVectorImpl<Register> &UpdatedDefs,
+                          GISelObserverWrapper &Observer) {
     unsigned Opcode = MI.getOpcode();
     assert(Opcode == TargetOpcode::G_ANYEXT || Opcode == TargetOpcode::G_ZEXT ||
            Opcode == TargetOpcode::G_SEXT);
@@ -392,7 +393,9 @@ class LegalizationArtifactCombiner {
         if (!isInstLegal({TargetOpcode::G_IMPLICIT_DEF, {DstTy}}))
           return false;
         LLVM_DEBUG(dbgs() << ".. Combine G_ANYEXT(G_IMPLICIT_DEF): " << MI;);
-        Builder.buildInstr(TargetOpcode::G_IMPLICIT_DEF, {DstReg}, {});
+        auto Impl = Builder.buildInstr(TargetOpcode::G_IMPLICIT_DEF, {DstTy}, {});
+        replaceRegOrBuildCopy(DstReg, Impl.getReg(0), MRI, Builder, UpdatedDefs,
+                              Observer);
         UpdatedDefs.push_back(DstReg);
       } else {
         // G_[SZ]EXT (G_IMPLICIT_DEF) -> G_CONSTANT 0 because the top
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-ext-debugloc.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-ext-debugloc.mir
index 7296e10b4a61e3..e16faa6ba9e6b8 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-ext-debugloc.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-ext-debugloc.mir
@@ -2,7 +2,7 @@
 
 # Check that when we combine ZEXT/ANYEXT we assign the correct location.
 # CHECK: !8 = !DILocation(line: 23, column: 5, scope: !4)
-# CHECK:  G_AND %14, %15, debug-location !8
+# CHECK:  G_AND %16, %15, debug-location !8
 
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-build-vector.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-build-vector.mir
index a63d8b9c137725..6b9b08e2f9f4d6 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-build-vector.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-build-vector.mir
@@ -141,8 +141,7 @@ body: |
   bb.0:
     ; CHECK-LABEL: name: widen_v2s8
     ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[DEF]](s32)
+    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[DEF]](s32), [[DEF]](s32)
     ; CHECK-NEXT: $d0 = COPY [[BUILD_VECTOR]](<2 x s32>)
     ; CHECK-NEXT: RET_ReallyLR
     %0:_(s8) = G_IMPLICIT_DEF
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-concat-vectors.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-concat-vectors.mir
index 87bbbee35d6d62..5527cbfb682b42 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-concat-vectors.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-concat-vectors.mir
@@ -75,10 +75,7 @@ body:             |
     ; CHECK-NEXT: %b:_(s32) = G_LOAD %a(p0) :: (load (s32))
     ; CHECK-NEXT: %c:_(<4 x s8>) = G_BITCAST %b(s32)
     ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY [[DEF]](s16)
-    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY [[DEF]](s16)
-    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s16) = COPY [[DEF]](s16)
-    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[COPY]](s16), [[COPY1]](s16), [[COPY2]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16)
+    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16)
     ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[BUILD_VECTOR]](<8 x s16>)
     ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s8>), [[UV1:%[0-9]+]]:_(<4 x s8>) = G_UNMERGE_VALUES [[TRUNC]](<8 x s8>)
     ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST %c(<4 x s8>)
@@ -113,8 +110,7 @@ body:             |
     ; CHECK-NEXT: %b:_(s32) = G_LOAD %a(p0) :: (load (s32))
     ; CHECK-NEXT: %c:_(<2 x s16>) = G_BITCAST %b(s32)
     ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32)
+    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32)
     ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[BUILD_VECTOR]](<4 x s32>)
     ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[TRUNC]](<4 x s16>)
     ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST %c(<2 x s16>)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
index 942bb60f5c0623..eb9c3ff60c7045 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
@@ -67,258 +67,196 @@ body: |
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x2
     ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
-    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
     ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C1]](s64)
     ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
     ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
     ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL]]
-    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
     ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C2]](s64)
     ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
-    ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+    ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
     ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C3]](s64)
     ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
-    ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
+    ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
     ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C4]](s64)
     ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[SHL3]]
-    ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
+    ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
     ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C5]](s64)
     ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
-    ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C]]
+    ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
     ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C6]](s64)
     ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
-    ; CHECK-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C]]
+    ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
     ; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C7]](s64)
     ; CHECK-NEXT: [[OR6:%[0-9]+]]:_(s32) = G_OR [[OR5]], [[SHL6]]
     ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[OR6]](s32)
-    ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C]]
+    ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C1]](s64)
-    ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
+    ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[OR7:%[0-9]+]]:_(s32) = G_OR [[AND9]], [[SHL7]]
-    ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]
+    ; CHECK-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C2]](s64)
     ; CHECK-NEXT: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
-    ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C]]
+    ; CHECK-NEXT: [[AND11:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C3]](s64)
     ; CHECK-NEXT: [[OR9:%[0-9]+]]:_(s32) = G_OR [[OR8]], [[SHL9]]
-    ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C]]
+    ; CHECK-NEXT: [[AND12:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND12]], [[C4]](s64)
     ; CHECK-NEXT: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
-    ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C]]
+    ; CHECK-NEXT: [[AND13:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C5]](s64)
     ; CHECK-NEXT: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
-    ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C]]
+    ; CHECK-NEXT: [[AND14:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C6]](s64)
     ; CHECK-NEXT: [[OR12:%[0-9]+]]:_(s32) = G_OR [[OR11]], [[SHL12]]
-    ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C]]
+    ; CHECK-NEXT: [[AND15:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C7]](s64)
     ; CHECK-NEXT: [[OR13:%[0-9]+]]:_(s32) = G_OR [[OR12]], [[SHL13]]
     ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[OR13]](s32)
-    ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C]]
+    ; CHECK-NEXT: [[AND16:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND16]], [[C1]](s64)
-    ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C]]
+    ; CHECK-NEXT: [[AND17:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[OR14:%[0-9]+]]:_(s32) = G_OR [[AND17]], [[SHL14]]
-    ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C]]
+    ; CHECK-NEXT: [[AND18:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND18]], [[C2]](s64)
     ; CHECK-NEXT: [[OR15:%[0-9]+]]:_(s32) = G_OR [[OR14]], [[SHL15]]
-    ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C]]
+    ; CHECK-NEXT: [[AND19:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL16:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[C3]](s64)
     ; CHECK-NEXT: [[OR16:%[0-9]+]]:_(s32) = G_OR [[OR15]], [[SHL16]]
-    ; CHECK-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND20:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C]]
+    ; CHECK-NEXT: [[AND20:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL17:%[0-9]+]]:_(s32) = G_SHL [[AND20]], [[C4]](s64)
     ; CHECK-NEXT: [[OR17:%[0-9]+]]:_(s32) = G_OR [[OR16]], [[SHL17]]
-    ; CHECK-NEXT: [[COPY22:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C]]
+    ; CHECK-NEXT: [[AND21:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL18:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[C5]](s64)
     ; CHECK-NEXT: [[OR18:%[0-9]+]]:_(s32) = G_OR [[OR17]], [[SHL18]]
-    ; CHECK-NEXT: [[COPY23:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C]]
+    ; CHECK-NEXT: [[AND22:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL19:%[0-9]+]]:_(s32) = G_SHL [[AND22]], [[C6]](s64)
     ; CHECK-NEXT: [[OR19:%[0-9]+]]:_(s32) = G_OR [[OR18]], [[SHL19]]
-    ; CHECK-NEXT: [[COPY24:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C]]
+    ; CHECK-NEXT: [[AND23:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL20:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[C7]](s64)
     ; CHECK-NEXT: [[OR20:%[0-9]+]]:_(s32) = G_OR [[OR19]], [[SHL20]]
     ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[OR20]](s32)
-    ; CHECK-NEXT: [[COPY25:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND24:%[0-9]+]]:_(s32) = G_AND [[COPY25]], [[C]]
+    ; CHECK-NEXT: [[AND24:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL21:%[0-9]+]]:_(s32) = G_SHL [[AND24]], [[C1]](s64)
-    ; CHECK-NEXT: [[COPY26:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND25:%[0-9]+]]:_(s32) = G_AND [[COPY26]], [[C]]
+    ; CHECK-NEXT: [[AND25:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[OR21:%[0-9]+]]:_(s32) = G_OR [[AND25]], [[SHL21]]
-    ; CHECK-NEXT: [[COPY27:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND26:%[0-9]+]]:_(s32) = G_AND [[COPY27]], [[C]]
+    ; CHECK-NEXT: [[AND26:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL22:%[0-9]+]]:_(s32) = G_SHL [[AND26]], [[C2]](s64)
     ; CHECK-NEXT: [[OR22:%[0-9]+]]:_(s32) = G_OR [[OR21]], [[SHL22]]
-    ; CHECK-NEXT: [[COPY28:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND27:%[0-9]+]]:_(s32) = G_AND [[COPY28]], [[C]]
+    ; CHECK-NEXT: [[AND27:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL23:%[0-9]+]]:_(s32) = G_SHL [[AND27]], [[C3]](s64)
     ; CHECK-NEXT: [[OR23:%[0-9]+]]:_(s32) = G_OR [[OR22]], [[SHL23]]
-    ; CHECK-NEXT: [[COPY29:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND28:%[0-9]+]]:_(s32) = G_AND [[COPY29]], [[C]]
+    ; CHECK-NEXT: [[AND28:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL24:%[0-9]+]]:_(s32) = G_SHL [[AND28]], [[C4]](s64)
     ; CHECK-NEXT: [[OR24:%[0-9]+]]:_(s32) = G_OR [[OR23]], [[SHL24]]
-    ; CHECK-NEXT: [[COPY30:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND29:%[0-9]+]]:_(s32) = G_AND [[COPY30]], [[C]]
+    ; CHECK-NEXT: [[AND29:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL25:%[0-9]+]]:_(s32) = G_SHL [[AND29]], [[C5]](s64)
     ; CHECK-NEXT: [[OR25:%[0-9]+]]:_(s32) = G_OR [[OR24]], [[SHL25]]
-    ; CHECK-NEXT: [[COPY31:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND30:%[0-9]+]]:_(s32) = G_AND [[COPY31]], [[C]]
+    ; CHECK-NEXT: [[AND30:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL26:%[0-9]+]]:_(s32) = G_SHL [[AND30]], [[C6]](s64)
     ; CHECK-NEXT: [[OR26:%[0-9]+]]:_(s32) = G_OR [[OR25]], [[SHL26]]
-    ; CHECK-NEXT: [[COPY32:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND31:%[0-9]+]]:_(s32) = G_AND [[COPY32]], [[C]]
+    ; CHECK-NEXT: [[AND31:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL27:%[0-9]+]]:_(s32) = G_SHL [[AND31]], [[C7]](s64)
     ; CHECK-NEXT: [[OR27:%[0-9]+]]:_(s32) = G_OR [[OR26]], [[SHL27]]
     ; CHECK-NEXT: [[TRUNC4:%[0-9]+]]:_(s8) = G_TRUNC [[OR27]](s32)
-    ; CHECK-NEXT: [[COPY33:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND32:%[0-9]+]]:_(s32) = G_AND [[COPY33]], [[C]]
+    ; CHECK-NEXT: [[AND32:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL28:%[0-9]+]]:_(s32) = G_SHL [[AND32]], [[C1]](s64)
-    ; CHECK-NEXT: [[COPY34:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND33:%[0-9]+]]:_(s32) = G_AND [[COPY34]], [[C]]
+    ; CHECK-NEXT: [[AND33:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[OR28:%[0-9]+]]:_(s32) = G_OR [[AND33]], [[SHL28]]
-    ; CHECK-NEXT: [[COPY35:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND34:%[0-9]+]]:_(s32) = G_AND [[COPY35]], [[C]]
+    ; CHECK-NEXT: [[AND34:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL29:%[0-9]+]]:_(s32) = G_SHL [[AND34]], [[C2]](s64)
     ; CHECK-NEXT: [[OR29:%[0-9]+]]:_(s32) = G_OR [[OR28]], [[SHL29]]
-    ; CHECK-NEXT: [[COPY36:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND35:%[0-9]+]]:_(s32) = G_AND [[COPY36]], [[C]]
+    ; CHECK-NEXT: [[AND35:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL30:%[0-9]+]]:_(s32) = G_SHL [[AND35]], [[C3]](s64)
     ; CHECK-NEXT: [[OR30:%[0-9]+]]:_(s32) = G_OR [[OR29]], [[SHL30]]
-    ; CHECK-NEXT: [[COPY37:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND36:%[0-9]+]]:_(s32) = G_AND [[COPY37]], [[C]]
+    ; CHECK-NEXT: [[AND36:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL31:%[0-9]+]]:_(s32) = G_SHL [[AND36]], [[C4]](s64)
     ; CHECK-NEXT: [[OR31:%[0-9]+]]:_(s32) = G_OR [[OR30]], [[SHL31]]
-    ; CHECK-NEXT: [[COPY38:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND37:%[0-9]+]]:_(s32) = G_AND [[COPY38]], [[C]]
+    ; CHECK-NEXT: [[AND37:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL32:%[0-9]+]]:_(s32) = G_SHL [[AND37]], [[C5]](s64)
     ; CHECK-NEXT: [[OR32:%[0-9]+]]:_(s32) = G_OR [[OR31]], [[SHL32]]
-    ; CHECK-NEXT: [[COPY39:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND38:%[0-9]+]]:_(s32) = G_AND [[COPY39]], [[C]]
+    ; CHECK-NEXT: [[AND38:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL33:%[0-9]+]]:_(s32) = G_SHL [[AND38]], [[C6]](s64)
     ; CHECK-NEXT: [[OR33:%[0-9]+]]:_(s32) = G_OR [[OR32]], [[SHL33]]
-    ; CHECK-NEXT: [[COPY40:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND39:%[0-9]+]]:_(s32) = G_AND [[COPY40]], [[C]]
+    ; CHECK-NEXT: [[AND39:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
     ; CHECK-NEXT: [[SHL34:%[0-9]+]]:_(s32) = G_SHL [[AND39]], [[C7]](s64)
     ; CHECK-NEXT: [[OR34:%[0-9]+]]:_(s32) = G_OR [[OR33]], [[SHL34]]
     ; CHECK-NEXT: [[TRUNC5:%[0-9]+]]:_(s8) = G_TRUNC [[OR34]](s32)
-    ; CHECK-NEXT: [[COPY41:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[AND40:%[0-9]+]]:_(s32) = G_AND [[COPY41]], [...
[truncated]

@github-actions GitHub Actions
Copy link

github-actions bot commented Dec 12, 2024 •
edited
Loading

✅ With the latest revision this PR passed the C/C++ code formatter.

@arsenm
Copy link
Contributor

arsenm commented Dec 12, 2024

Make clang-format happy by using buildUndef instead of the low level buildInstr?

@davemgreen
[GlobalISel] Use replaceRegOrBuildCopy when legalizer-combining anyex…
4fdde3b 
…t(undef).

This avoids the unnecessary creation of some COPY nodes created from the CSE
builder.
@davemgreen davemgreen force-pushed the gh-gi-usereplaceRegOrBuildCopy branch from 566f4a5 to 4fdde3b Compare December 13, 2024 08:28
@davemgreen davemgreen merged commit 3d6b2d4 into llvm:main Dec 13, 2024
5 of 8 checks passed
@davemgreen davemgreen deleted the gh-gi-usereplaceRegOrBuildCopy branch December 13, 2024 08:39
@llvm-ci
Copy link
Collaborator

llvm-ci commented Dec 13, 2024

LLVM Buildbot has detected a new failure on builder llvm-clang-aarch64-darwin running on doug-worker-4 while building llvm at step 6 "test-build-unified-tree-check-all".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/190/builds/11292

Here is the relevant piece of the build log for the reference 
Step 6 (test-build-unified-tree-check-all) failure: test (failure)
...
PASS: lld :: MachO/arm64-objc-stubs-dyn.s (79802 of 80345)
PASS: lld :: MachO/arm64-objc-stubs-fix.s (79803 of 80345)
PASS: lld :: MachO/arm64-objc-stubs.s (79804 of 80345)
PASS: lld :: MachO/arm64-reloc-got-load.s (79805 of 80345)
PASS: lld :: MachO/arm64-reloc-pointer-to-got.s (79806 of 80345)
PASS: lld :: MachO/arm64-reloc-tlv-load.s (79807 of 80345)
PASS: lld :: MachO/arm64-relocs.s (79808 of 80345)
PASS: lld :: MachO/arm64-stubs.s (79809 of 80345)
PASS: lld :: ELF/aarch64-thunk-reuse2.s (79810 of 80345)
UNRESOLVED: lld :: MachO/arm64-thunk-starvation.s (79811 of 80345)
******************** TEST 'lld :: MachO/arm64-thunk-starvation.s' FAILED ********************
Exception during script execution:
Traceback (most recent call last):
  File "/Users/buildbot/buildbot-root/aarch64-darwin/llvm-project/llvm/utils/lit/lit/worker.py", line 76, in _execute_test_handle_errors
    result = test.config.test_format.execute(test, lit_config)
  File "/Users/buildbot/buildbot-root/aarch64-darwin/llvm-project/llvm/utils/lit/lit/formats/shtest.py", line 29, in execute
    return lit.TestRunner.executeShTest(
  File "/Users/buildbot/buildbot-root/aarch64-darwin/llvm-project/llvm/utils/lit/lit/TestRunner.py", line 2326, in executeShTest
    return _runShTest(test, litConfig, useExternalSh, script, tmpBase)
  File "/Users/buildbot/buildbot-root/aarch64-darwin/llvm-project/llvm/utils/lit/lit/TestRunner.py", line 2270, in _runShTest
    res = runOnce(execdir)
  File "/Users/buildbot/buildbot-root/aarch64-darwin/llvm-project/llvm/utils/lit/lit/TestRunner.py", line 2244, in runOnce
    res = executeScript(test, litConfig, tmpBase, scriptCopy, execdir)
  File "/Users/buildbot/buildbot-root/aarch64-darwin/llvm-project/llvm/utils/lit/lit/TestRunner.py", line 1210, in executeScript
    f = open(script, mode, **open_kwargs)
OSError: [Errno 28] No space left on device: '/Users/buildbot/buildbot-root/aarch64-darwin/build/tools/lld/test/MachO/Output/arm64-thunk-starvation.s.script'


********************
UNRESOLVED: lld :: MachO/arm64-thunk-visibility.s (79812 of 80345)
******************** TEST 'lld :: MachO/arm64-thunk-visibility.s' FAILED ********************
Exception during script execution:
Traceback (most recent call last):
  File "/Users/buildbot/buildbot-root/aarch64-darwin/llvm-project/llvm/utils/lit/lit/worker.py", line 76, in _execute_test_handle_errors
    result = test.config.test_format.execute(test, lit_config)
  File "/Users/buildbot/buildbot-root/aarch64-darwin/llvm-project/llvm/utils/lit/lit/formats/shtest.py", line 29, in execute
    return lit.TestRunner.executeShTest(
  File "/Users/buildbot/buildbot-root/aarch64-darwin/llvm-project/llvm/utils/lit/lit/TestRunner.py", line 2326, in executeShTest
    return _runShTest(test, litConfig, useExternalSh, script, tmpBase)
  File "/Users/buildbot/buildbot-root/aarch64-darwin/llvm-project/llvm/utils/lit/lit/TestRunner.py", line 2270, in _runShTest
    res = runOnce(execdir)
  File "/Users/buildbot/buildbot-root/aarch64-darwin/llvm-project/llvm/utils/lit/lit/TestRunner.py", line 2244, in runOnce
    res = executeScript(test, litConfig, tmpBase, scriptCopy, execdir)
  File "/Users/buildbot/buildbot-root/aarch64-darwin/llvm-project/llvm/utils/lit/lit/TestRunner.py", line 1210, in executeScript
    f = open(script, mode, **open_kwargs)
OSError: [Errno 28] No space left on device: '/Users/buildbot/buildbot-root/aarch64-darwin/build/tools/lld/test/MachO/Output/arm64-thunk-visibility.s.script'


********************

davemgreen added a commit to davemgreen/llvm-project that referenced this pull request Dec 13, 2024
@davemgreen
[GlobalISel] Use replaceRegOrBuildCopy when legalizer-combining s/zex…
79dfc49 
…t(undef)

Similar to llvm#119721, this helps remove some of the COPYs created by the CSE
builder.
@davemgreen davemgreen mentioned this pull request Dec 13, 2024
Merged
davemgreen added a commit to davemgreen/llvm-project that referenced this pull request Dec 15, 2024
@davemgreen
[GlobalISel] Use replaceRegOrBuildCopy when legalizer-combining s/zex…
e46c525 
…t(undef)

Similar to llvm#119721, this helps remove some of the COPYs created by the CSE
builder.
davemgreen added a commit that referenced this pull request Dec 16, 2024
@davemgreen
[GlobalISel] Use replaceRegOrBuildCopy when legalizer-combining s/zex…
9ba7e2d 
…t(undef) (#119850)

Similar to #119721, this helps remove some of the COPYs created by the
CSE builder.
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Reviewers

@arsenm arsenm arsenm approved these changes

@aemerson aemerson Awaiting requested review from aemerson

@stuij stuij Awaiting requested review from stuij

Assignees
No one assigned
Labels
backend:AArch64 llvm:globalisel
Projects
None yet
Milestone
No milestone
Development

Successfully merging this pull request may close these issues.
4 participants
@davemgreen @llvmbot @arsenm @llvm-ci