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[RISCV] Rename suffixes on VCPOP/VMSBF/VMSET/etc pseudos. NFC #119785

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Merged
merged 1 commit into from
Dec 13, 2024
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Merged

[RISCV] Rename suffixes on VCPOP/VMSBF/VMSET/etc pseudos. NFC #119785

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24 changes: 12 additions & 12 deletions llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
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Expand Up @@ -1673,13 +1673,13 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
VMNANDOpcode = RISCV::PseudoVMNAND_MM_##suffix; \
VMSetOpcode = RISCV::PseudoVMSET_M_##suffix_b; \
break;
CASE_VMSLT_VMNAND_VMSET_OPCODES(LMUL_F8, MF8, B1)
CASE_VMSLT_VMNAND_VMSET_OPCODES(LMUL_F4, MF4, B2)
CASE_VMSLT_VMNAND_VMSET_OPCODES(LMUL_F2, MF2, B4)
CASE_VMSLT_VMNAND_VMSET_OPCODES(LMUL_F8, MF8, B64)
CASE_VMSLT_VMNAND_VMSET_OPCODES(LMUL_F4, MF4, B32)
CASE_VMSLT_VMNAND_VMSET_OPCODES(LMUL_F2, MF2, B16)
CASE_VMSLT_VMNAND_VMSET_OPCODES(LMUL_1, M1, B8)
CASE_VMSLT_VMNAND_VMSET_OPCODES(LMUL_2, M2, B16)
CASE_VMSLT_VMNAND_VMSET_OPCODES(LMUL_4, M4, B32)
CASE_VMSLT_VMNAND_VMSET_OPCODES(LMUL_8, M8, B64)
CASE_VMSLT_VMNAND_VMSET_OPCODES(LMUL_2, M2, B4)
CASE_VMSLT_VMNAND_VMSET_OPCODES(LMUL_4, M4, B2)
CASE_VMSLT_VMNAND_VMSET_OPCODES(LMUL_8, M8, B1)
#undef CASE_VMSLT_VMNAND_VMSET_OPCODES
}
SDValue SEW = CurDAG->getTargetConstant(
Expand Down Expand Up @@ -1751,13 +1751,13 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
VMSGTMaskOpcode = IsUnsigned ? RISCV::PseudoVMSGTU_VX_##suffix##_MASK \
: RISCV::PseudoVMSGT_VX_##suffix##_MASK; \
break;
CASE_VMSLT_OPCODES(LMUL_F8, MF8, B1)
CASE_VMSLT_OPCODES(LMUL_F4, MF4, B2)
CASE_VMSLT_OPCODES(LMUL_F2, MF2, B4)
CASE_VMSLT_OPCODES(LMUL_F8, MF8, B64)
CASE_VMSLT_OPCODES(LMUL_F4, MF4, B32)
CASE_VMSLT_OPCODES(LMUL_F2, MF2, B16)
CASE_VMSLT_OPCODES(LMUL_1, M1, B8)
CASE_VMSLT_OPCODES(LMUL_2, M2, B16)
CASE_VMSLT_OPCODES(LMUL_4, M4, B32)
CASE_VMSLT_OPCODES(LMUL_8, M8, B64)
CASE_VMSLT_OPCODES(LMUL_2, M2, B4)
CASE_VMSLT_OPCODES(LMUL_4, M4, B2)
CASE_VMSLT_OPCODES(LMUL_8, M8, B1)
#undef CASE_VMSLT_OPCODES
}
// Mask operations use the LMUL from the mask type.
Expand Down
12 changes: 6 additions & 6 deletions llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
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Expand Up @@ -415,13 +415,13 @@ class MTypeInfo<ValueType Mas, LMULInfo M, string Bx> {

defset list<MTypeInfo> AllMasks = {
// vbool<n>_t, <n> = SEW/LMUL, we assume SEW=8 and corresponding LMUL.
def : MTypeInfo<vbool64_t, V_MF8, "B1">;
def : MTypeInfo<vbool32_t, V_MF4, "B2">;
def : MTypeInfo<vbool16_t, V_MF2, "B4">;
def : MTypeInfo<vbool64_t, V_MF8, "B64">;
def : MTypeInfo<vbool32_t, V_MF4, "B32">;
def : MTypeInfo<vbool16_t, V_MF2, "B16">;
def : MTypeInfo<vbool8_t, V_M1, "B8">;
def : MTypeInfo<vbool4_t, V_M2, "B16">;
def : MTypeInfo<vbool2_t, V_M4, "B32">;
def : MTypeInfo<vbool1_t, V_M8, "B64">;
def : MTypeInfo<vbool4_t, V_M2, "B4">;
def : MTypeInfo<vbool2_t, V_M4, "B2">;
def : MTypeInfo<vbool1_t, V_M8, "B1">;
}

class VTypeInfoToWide<VTypeInfo vti, VTypeInfo wti> {
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/render-vlop-rv32.mir
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Expand Up @@ -11,8 +11,8 @@ body: |
bb.1:
; CHECK-LABEL: name: negative_vl
; CHECK: [[ADDI:%[0-9]+]]:gprnox0 = ADDI $x0, -2
; CHECK-NEXT: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 [[ADDI]], 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
; CHECK-NEXT: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 [[ADDI]], 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]]
; CHECK-NEXT: PseudoRET implicit $v0
%0:gprb(s32) = G_CONSTANT i32 -2
%1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
Expand All @@ -31,8 +31,8 @@ body: |
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10
; CHECK-NEXT: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 [[COPY]], 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
; CHECK-NEXT: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 [[COPY]], 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]]
; CHECK-NEXT: PseudoRET implicit $v0
%0:gprb(s32) = COPY $x10
%1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
Expand All @@ -48,8 +48,8 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: nonzero_vl
; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 1, 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
; CHECK: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 1, 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]]
; CHECK-NEXT: PseudoRET implicit $v0
%0:gprb(s32) = G_CONSTANT i32 1
%1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
Expand All @@ -65,8 +65,8 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: zero_vl
; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 0, 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
; CHECK: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 0, 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]]
; CHECK-NEXT: PseudoRET implicit $v0
%0:gprb(s32) = G_CONSTANT i32 0
%1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/render-vlop-rv64.mir
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Expand Up @@ -11,8 +11,8 @@ body: |
bb.1:
; CHECK-LABEL: name: negative_vl
; CHECK: [[ADDI:%[0-9]+]]:gprnox0 = ADDI $x0, -2
; CHECK-NEXT: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 [[ADDI]], 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
; CHECK-NEXT: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 [[ADDI]], 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]]
; CHECK-NEXT: PseudoRET implicit $v0
%0:gprb(s64) = G_CONSTANT i64 -2
%1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s64)
Expand All @@ -31,8 +31,8 @@ body: |
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10
; CHECK-NEXT: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 [[COPY]], 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
; CHECK-NEXT: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 [[COPY]], 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]]
; CHECK-NEXT: PseudoRET implicit $v0
%0:gprb(s64) = COPY $x10
%1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s64)
Expand All @@ -48,8 +48,8 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: nonzero_vl
; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 1, 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
; CHECK: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 1, 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]]
; CHECK-NEXT: PseudoRET implicit $v0
%0:gprb(s64) = G_CONSTANT i64 1
%1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s64)
Expand All @@ -65,8 +65,8 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: zero_vl
; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 0, 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
; CHECK: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 0, 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]]
; CHECK-NEXT: PseudoRET implicit $v0
%0:gprb(s64) = G_CONSTANT i64 0
%1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s64)
Expand Down
24 changes: 12 additions & 12 deletions llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv32.mir
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Expand Up @@ -10,8 +10,8 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splat_zero_nxv1i1
; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 -1, 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
; CHECK: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 -1, 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]]
; CHECK-NEXT: PseudoRET implicit $v0
%0:gprb(s32) = G_CONSTANT i32 -1
%1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
Expand All @@ -27,8 +27,8 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splat_zero_nxv2i1
; CHECK: [[PseudoVMCLR_M_B2_:%[0-9]+]]:vr = PseudoVMCLR_M_B2 -1, 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B2_]]
; CHECK: [[PseudoVMCLR_M_B32_:%[0-9]+]]:vr = PseudoVMCLR_M_B32 -1, 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B32_]]
; CHECK-NEXT: PseudoRET implicit $v0
%0:gprb(s32) = G_CONSTANT i32 -1
%1:vrb(<vscale x 2 x s1>) = G_VMCLR_VL %0(s32)
Expand All @@ -44,8 +44,8 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splat_zero_nxv4i1
; CHECK: [[PseudoVMCLR_M_B4_:%[0-9]+]]:vr = PseudoVMCLR_M_B4 -1, 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B4_]]
; CHECK: [[PseudoVMCLR_M_B16_:%[0-9]+]]:vr = PseudoVMCLR_M_B16 -1, 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B16_]]
; CHECK-NEXT: PseudoRET implicit $v0
%0:gprb(s32) = G_CONSTANT i32 -1
%1:vrb(<vscale x 4 x s1>) = G_VMCLR_VL %0(s32)
Expand Down Expand Up @@ -78,8 +78,8 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splat_zero_nxv16i1
; CHECK: [[PseudoVMCLR_M_B16_:%[0-9]+]]:vr = PseudoVMCLR_M_B16 -1, 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B16_]]
; CHECK: [[PseudoVMCLR_M_B4_:%[0-9]+]]:vr = PseudoVMCLR_M_B4 -1, 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B4_]]
; CHECK-NEXT: PseudoRET implicit $v0
%0:gprb(s32) = G_CONSTANT i32 -1
%1:vrb(<vscale x 16 x s1>) = G_VMCLR_VL %0(s32)
Expand All @@ -95,8 +95,8 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splat_zero_nxv32i1
; CHECK: [[PseudoVMCLR_M_B32_:%[0-9]+]]:vr = PseudoVMCLR_M_B32 -1, 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B32_]]
; CHECK: [[PseudoVMCLR_M_B2_:%[0-9]+]]:vr = PseudoVMCLR_M_B2 -1, 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B2_]]
; CHECK-NEXT: PseudoRET implicit $v0
%0:gprb(s32) = G_CONSTANT i32 -1
%1:vrb(<vscale x 32 x s1>) = G_VMCLR_VL %0(s32)
Expand All @@ -112,8 +112,8 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splat_zero_nxv64i1
; CHECK: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 -1, 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]]
; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 -1, 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
; CHECK-NEXT: PseudoRET implicit $v0
%0:gprb(s32) = G_CONSTANT i32 -1
%1:vrb(<vscale x 64 x s1>) = G_VMCLR_VL %0(s32)
Expand Down
24 changes: 12 additions & 12 deletions llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv64.mir
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Expand Up @@ -10,8 +10,8 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splat_zero_nxv1i1
; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 -1, 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
; CHECK: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 -1, 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]]
; CHECK-NEXT: PseudoRET implicit $v0
%0:gprb(s64) = G_CONSTANT i64 -1
%1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s64)
Expand All @@ -27,8 +27,8 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splat_zero_nxv2i1
; CHECK: [[PseudoVMCLR_M_B2_:%[0-9]+]]:vr = PseudoVMCLR_M_B2 -1, 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B2_]]
; CHECK: [[PseudoVMCLR_M_B32_:%[0-9]+]]:vr = PseudoVMCLR_M_B32 -1, 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B32_]]
; CHECK-NEXT: PseudoRET implicit $v0
%0:gprb(s64) = G_CONSTANT i64 -1
%1:vrb(<vscale x 2 x s1>) = G_VMCLR_VL %0(s64)
Expand All @@ -44,8 +44,8 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splat_zero_nxv4i1
; CHECK: [[PseudoVMCLR_M_B4_:%[0-9]+]]:vr = PseudoVMCLR_M_B4 -1, 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B4_]]
; CHECK: [[PseudoVMCLR_M_B16_:%[0-9]+]]:vr = PseudoVMCLR_M_B16 -1, 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B16_]]
; CHECK-NEXT: PseudoRET implicit $v0
%0:gprb(s64) = G_CONSTANT i64 -1
%1:vrb(<vscale x 4 x s1>) = G_VMCLR_VL %0(s64)
Expand Down Expand Up @@ -78,8 +78,8 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splat_zero_nxv16i1
; CHECK: [[PseudoVMCLR_M_B16_:%[0-9]+]]:vr = PseudoVMCLR_M_B16 -1, 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B16_]]
; CHECK: [[PseudoVMCLR_M_B4_:%[0-9]+]]:vr = PseudoVMCLR_M_B4 -1, 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B4_]]
; CHECK-NEXT: PseudoRET implicit $v0
%0:gprb(s64) = G_CONSTANT i64 -1
%1:vrb(<vscale x 16 x s1>) = G_VMCLR_VL %0(s64)
Expand All @@ -95,8 +95,8 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splat_zero_nxv32i1
; CHECK: [[PseudoVMCLR_M_B32_:%[0-9]+]]:vr = PseudoVMCLR_M_B32 -1, 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B32_]]
; CHECK: [[PseudoVMCLR_M_B2_:%[0-9]+]]:vr = PseudoVMCLR_M_B2 -1, 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B2_]]
; CHECK-NEXT: PseudoRET implicit $v0
%0:gprb(s64) = G_CONSTANT i64 -1
%1:vrb(<vscale x 32 x s1>) = G_VMCLR_VL %0(s64)
Expand All @@ -112,8 +112,8 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splat_zero_nxv64i1
; CHECK: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 -1, 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]]
; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 -1, 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
; CHECK-NEXT: PseudoRET implicit $v0
%0:gprb(s64) = G_CONSTANT i64 -1
%1:vrb(<vscale x 64 x s1>) = G_VMCLR_VL %0(s64)
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -512,9 +512,9 @@ body: |
; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0 killed $x0, 23 /* e32, mf2, tu, mu */, implicit-def $vl, implicit-def $vtype, implicit $vl
; CHECK-NEXT: [[PseudoVLE32_V_MF2_MASK:%[0-9]+]]:vrnov0 = PseudoVLE32_V_MF2_MASK [[PseudoVMV_V_I_MF2_]], [[COPY]], $v0, -1, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0 killed $x0, 197 /* e8, mf8, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl
; CHECK-NEXT: [[PseudoVCPOP_M_B1_:%[0-9]+]]:gpr = PseudoVCPOP_M_B1 [[PseudoVMSEQ_VI_MF2_]], -1, 0 /* e8 */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[PseudoVCPOP_M_B64_:%[0-9]+]]:gpr = PseudoVCPOP_M_B64 [[PseudoVMSEQ_VI_MF2_]], -1, 0 /* e8 */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr = IMPLICIT_DEF
; CHECK-NEXT: BEQ [[PseudoVCPOP_M_B1_]], $x0, %bb.3
; CHECK-NEXT: BEQ [[PseudoVCPOP_M_B64_]], $x0, %bb.3
; CHECK-NEXT: PseudoBR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
Expand Down Expand Up @@ -543,7 +543,7 @@ body: |
%5:vmv0 = PseudoVMSEQ_VI_MF2 killed %3, 0, -1, 5
$v0 = COPY %5
%6:vrnov0 = PseudoVLE32_V_MF2_MASK %4, killed %0, $v0, -1, 5, 0
%7:gpr = PseudoVCPOP_M_B1 %5, -1, 0
%7:gpr = PseudoVCPOP_M_B64 %5, -1, 0
%8:gpr = COPY $x0
BEQ killed %7, %8, %bb.3
PseudoBR %bb.2
Expand Down Expand Up @@ -906,8 +906,8 @@ body: |
; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl
; CHECK-NEXT: [[PseudoVADD_VX_M1_:%[0-9]+]]:vr = PseudoVADD_VX_M1 undef $noreg, [[PseudoVID_V_M1_]], [[ADD]], -1, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[PseudoVMSLTU_VX_M1_:%[0-9]+]]:vr = PseudoVMSLTU_VX_M1 [[PseudoVADD_VX_M1_]], [[COPY1]], -1, 6 /* e64 */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[PseudoVCPOP_M_B1_:%[0-9]+]]:gpr = PseudoVCPOP_M_B1 [[PseudoVMSLTU_VX_M1_]], -1, 0 /* e8 */, implicit $vl, implicit $vtype
; CHECK-NEXT: BEQ [[PseudoVCPOP_M_B1_]], $x0, %bb.3
; CHECK-NEXT: [[PseudoVCPOP_M_B64_:%[0-9]+]]:gpr = PseudoVCPOP_M_B64 [[PseudoVMSLTU_VX_M1_]], -1, 0 /* e8 */, implicit $vl, implicit $vtype
; CHECK-NEXT: BEQ [[PseudoVCPOP_M_B64_]], $x0, %bb.3
; CHECK-NEXT: PseudoBR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
Expand Down Expand Up @@ -952,7 +952,7 @@ body: |
%61:gpr = ADD %12, %26
%27:vr = PseudoVADD_VX_M1 undef $noreg, %10, killed %61, -1, 6, 0
%62:vr = PseudoVMSLTU_VX_M1 %27, %11, -1, 6
%63:gpr = PseudoVCPOP_M_B1 %62, -1, 0
%63:gpr = PseudoVCPOP_M_B64 %62, -1, 0
%64:gpr = COPY $x0
BEQ killed %63, %64, %bb.3
PseudoBR %bb.2
Expand Down
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