[RISCV] Fix typo in CV_SH_rr_inc pattern

[PhilippvK]

This typo in https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td#L701:L701 caused a compiler crash in 'RISC-V Assembly Printer' because CV_SH_ri_inc was selected, leading to getImmOpValue being called for a register operand.

This bug did not affect the Assembler output and therefore does not trigger any existing unit tests, but is visible by examining the final MIR function.

I came up with a minimal test, but I am unsure how to integrate this into llvm/test/CodeGen/RISCV/xcvmem.ll while still using utils/update_llc_test_checks.py. I would be happy I you could provide a hint on how both CHECK_ASM as well as CHECK_MIR lines could be generated automatically in the same test.

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O3 -mtriple=riscv32 -mattr=+xcvmem -verify-machineinstrs -stop-after=instruction-select < %s \
; RUN:   | FileCheck %s --check-prefixes=CHECK_MIR

define i16* @sh_ri_inc(i16* %a, i16 %b) {
; CHECK_MIR: CV_SH_ri_inc
  store i16 %b, i16* %a
  %1 = getelementptr i16, i16* %a, i32 42
  ret i16* %1
}

define i16* @sh_rr_inc(i16* %a, i16 %b, i32 %c) {
; CHECK_MIR: CV_SH_rr_inc
  store i16 %b, i16* %a
  %1 = getelementptr i16, i16* %a, i32 %c
  ret i16* %1
}

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[llvmbot]

@llvm/pr-subscribers-backend-risc-v

Author: Philipp van Kempen (PhilippvK)

Changes

This typo in https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td#L701:L701 caused a compiler crash in 'RISC-V Assembly Printer' because CV_SH_ri_inc was selected, leading to getImmOpValue being called for a register operand.

This bug did not affect the Assembler output and therefore does not trigger any existing unit tests, but is visible by examining the final MIR function.

I came up with a minimal test, but I am unsure how to integrate this into llvm/test/CodeGen/RISCV/xcvmem.ll while still using utils/update_llc_test_checks.py. I would be happy I you could provide a hint on how both CHECK_ASM as well as CHECK_MIR lines could be generated automatically in the same test.

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O3 -mtriple=riscv32 -mattr=+xcvmem -verify-machineinstrs -stop-after=instruction-select < %s \
; RUN:   | FileCheck %s --check-prefixes=CHECK_MIR

define i16* @<!-- -->sh_ri_inc(i16* %a, i16 %b) {
; CHECK_MIR: CV_SH_ri_inc
  store i16 %b, i16* %a
  %1 = getelementptr i16, i16* %a, i32 42
  ret i16* %1
}

define i16* @<!-- -->sh_rr_inc(i16* %a, i16 %b, i32 %c) {
; CHECK_MIR: CV_SH_rr_inc
  store i16 %b, i16* %a
  %1 = getelementptr i16, i16* %a, i32 %c
  ret i16* %1
}

---

Full diff: https://github.com/llvm/llvm-project/pull/120246.diff

1 Files Affected:

• (modified) llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td (+1-1)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
index 4478e246111080..b98934d8c63964 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
@@ -698,7 +698,7 @@ let Predicates = [HasVendorXCVmem, IsRV32], AddedComplexity = 1 in {
   def : CVStriPat<post_store, CV_SW_ri_inc>;
 
   def : CVStrriPat<post_truncsti8, CV_SB_rr_inc>;
-  def : CVStrriPat<post_truncsti16, CV_SH_ri_inc>;
+  def : CVStrriPat<post_truncsti16, CV_SH_rr_inc>;
   def : CVStrriPat<post_store, CV_SW_rr_inc>;
 
   def : CVStrrPat<truncstorei8, CV_SB_rr>;

[lenary]

You're almost right with your file header, but not quite.

You need to make sure that the -stop-after= is naming the right pass. I think instruction-select is the GlobalISel name, and you want riscv-isel for the default pipeline (SelectionDAG).

I'm not sure you can use update_llc_test_checks.py with MIR output - you want update_mir_test_checks.py. I think a test ending at selection only would be enough for this change, because I don't think it's possible to mix update_mir_test_checks.py (mir output) and update_llc_test_checks.py (asm output).

[topperc]

I just posted #120286 which I think removes the need to test MIR for this. If we agree, we can land just the .td change in this patch without any test and I'll land the verifier fix after.

[PhilippvK]

You're almost right with your file header, but not quite.

You need to make sure that the -stop-after= is naming the right pass. I think instruction-select is the GlobalISel name, and you want riscv-isel for the default pipeline (SelectionDAG).

I'm not sure you can use update_llc_test_checks.py with MIR output - you want update_mir_test_checks.py. I think a test ending at selection only would be enough for this change, because I don't think it's possible to mix update_mir_test_checks.py (mir output) and update_llc_test_checks.py (asm output).

@lenary Thank you for the hint. I wanted to avoid adding a completely new set of test files for testing the XCV* extensions on the MIR level.

I just posted #120286 which I think removes the need to test MIR for this. If we agree, we can land just the .td change in this patch without any test and I'll land the verifier fix after.

@topperc That actually sounds like the best solution. Your fix makes a lot of sense, thank you! Can I expect this fix to be backported to LLVM19.1.6?

[topperc]

You're almost right with your file header, but not quite.
You need to make sure that the -stop-after= is naming the right pass. I think instruction-select is the GlobalISel name, and you want riscv-isel for the default pipeline (SelectionDAG).
I'm not sure you can use update_llc_test_checks.py with MIR output - you want update_mir_test_checks.py. I think a test ending at selection only would be enough for this change, because I don't think it's possible to mix update_mir_test_checks.py (mir output) and update_llc_test_checks.py (asm output).

@lenary Thank you for the hint. I wanted to avoid adding a completely new set of test files for testing the XCV* extensions on the MIR level.

I just posted #120286 which I think removes the need to test MIR for this. If we agree, we can land just the .td change in this patch without any test and I'll land the verifier fix after.

@topperc That actually sounds like the best solution. Your fix makes a lot of sense, thank you! Can I expect this fix to be backported to LLVM19.1.6?

I think we can backport the .td change to 19.1.6. I'll have to check if my verifier patch can be backported.

[topperc]

LGTM

[topperc]

@PhilippvK I assume you need me to commit this?

[PhilippvK]

@topperc Yes, that would be great!

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[topperc]

/cherry-pick e8ce6c4

[llvmbot]

/pull-request #120296