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[AArch64] Verify consecutive vector registers in tbl, tbx #120262

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Dec 20, 2024
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[AArch64] Verify consecutive vector registers in tbl, tbx #120262

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32 changes: 16 additions & 16 deletions llvm/lib/Target/AArch64/AArch64InstrFormats.td
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Original file line number Diff line number Diff line change
Expand Up @@ -8528,28 +8528,28 @@ multiclass SIMDTableLookup<bit op, string asm> {

def : SIMDTableLookupAlias<asm # ".8b",
!cast<Instruction>(NAME#"v8i8One"),
V64, VecListOne128>;
V64, VecListOneConsecutive128>;
def : SIMDTableLookupAlias<asm # ".8b",
!cast<Instruction>(NAME#"v8i8Two"),
V64, VecListTwo128>;
V64, VecListTwoConsecutive128>;
def : SIMDTableLookupAlias<asm # ".8b",
!cast<Instruction>(NAME#"v8i8Three"),
V64, VecListThree128>;
V64, VecListThreeConsecutive128>;
def : SIMDTableLookupAlias<asm # ".8b",
!cast<Instruction>(NAME#"v8i8Four"),
V64, VecListFour128>;
V64, VecListFourConsecutive128>;
def : SIMDTableLookupAlias<asm # ".16b",
!cast<Instruction>(NAME#"v16i8One"),
V128, VecListOne128>;
V128, VecListOneConsecutive128>;
def : SIMDTableLookupAlias<asm # ".16b",
!cast<Instruction>(NAME#"v16i8Two"),
V128, VecListTwo128>;
V128, VecListTwoConsecutive128>;
def : SIMDTableLookupAlias<asm # ".16b",
!cast<Instruction>(NAME#"v16i8Three"),
V128, VecListThree128>;
V128, VecListThreeConsecutive128>;
def : SIMDTableLookupAlias<asm # ".16b",
!cast<Instruction>(NAME#"v16i8Four"),
V128, VecListFour128>;
V128, VecListFourConsecutive128>;
}

multiclass SIMDTableLookupTied<bit op, string asm> {
Expand All @@ -8572,28 +8572,28 @@ multiclass SIMDTableLookupTied<bit op, string asm> {

def : SIMDTableLookupAlias<asm # ".8b",
!cast<Instruction>(NAME#"v8i8One"),
V64, VecListOne128>;
V64, VecListOneConsecutive128>;
def : SIMDTableLookupAlias<asm # ".8b",
!cast<Instruction>(NAME#"v8i8Two"),
V64, VecListTwo128>;
V64, VecListTwoConsecutive128>;
def : SIMDTableLookupAlias<asm # ".8b",
!cast<Instruction>(NAME#"v8i8Three"),
V64, VecListThree128>;
V64, VecListThreeConsecutive128>;
def : SIMDTableLookupAlias<asm # ".8b",
!cast<Instruction>(NAME#"v8i8Four"),
V64, VecListFour128>;
V64, VecListFourConsecutive128>;
def : SIMDTableLookupAlias<asm # ".16b",
!cast<Instruction>(NAME#"v16i8One"),
V128, VecListOne128>;
V128, VecListOneConsecutive128>;
def : SIMDTableLookupAlias<asm # ".16b",
!cast<Instruction>(NAME#"v16i8Two"),
V128, VecListTwo128>;
V128, VecListTwoConsecutive128>;
def : SIMDTableLookupAlias<asm # ".16b",
!cast<Instruction>(NAME#"v16i8Three"),
V128, VecListThree128>;
V128, VecListThreeConsecutive128>;
def : SIMDTableLookupAlias<asm # ".16b",
!cast<Instruction>(NAME#"v16i8Four"),
V128, VecListFour128>;
V128, VecListFourConsecutive128>;
}

//----------------------------------------------------------------------------
Expand Down
13 changes: 12 additions & 1 deletion llvm/lib/Target/AArch64/AArch64RegisterInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -646,7 +646,7 @@ class TypedVecListRegOperand<RegisterClass Reg, int lanes, string eltsize>
# eltsize # "'>">;

multiclass VectorList<int count, RegisterClass Reg64, RegisterClass Reg128> {
// With implicit types (probably on instruction instead). E.g. { v0, v1 }
// With implicit types (probably on instruction instead). E.g. { v0, v1 } or {v0, v2, v4}.
def _64AsmOperand : AsmOperandClass {
let Name = NAME # "64";
let PredicateMethod = "isImplicitlyTypedVectorList<RegKind::NeonVector, " # count # ">";
Expand All @@ -667,6 +667,17 @@ multiclass VectorList<int count, RegisterClass Reg64, RegisterClass Reg128> {
let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_128AsmOperand");
}

// With implicit types (probably on instruction instead), consecutive registers. E.g. { v0, v1, v2 }
def _Consecutive128AsmOperand : AsmOperandClass {
let Name = NAME # "Consecutive128";
let PredicateMethod = "isImplicitlyTypedVectorList<RegKind::NeonVector, " # count # ", true>";
let RenderMethod = "addVectorListOperands<AArch64Operand::VecListIdx_QReg, " # count # ", true>";
}

def "Consecutive128" : RegisterOperand<Reg128, "printImplicitlyTypedVectorList"> {
let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_Consecutive128AsmOperand");
}

// 64-bit register lists with explicit type.

// { v0.8b, v1.8b }
Expand Down
10 changes: 7 additions & 3 deletions llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1445,11 +1445,12 @@ class AArch64Operand : public MCParsedAsmOperand {

/// Is this a vector list with the type implicit (presumably attached to the
/// instruction itself)?
template <RegKind VectorKind, unsigned NumRegs>
template <RegKind VectorKind, unsigned NumRegs, bool IsConsecutive = false>
bool isImplicitlyTypedVectorList() const {
return Kind == k_VectorList && VectorList.Count == NumRegs &&
VectorList.NumElements == 0 &&
VectorList.RegisterKind == VectorKind;
VectorList.RegisterKind == VectorKind &&
(!IsConsecutive || (VectorList.Stride == 1));
}

template <RegKind VectorKind, unsigned NumRegs, unsigned NumElements,
Expand Down Expand Up @@ -1864,9 +1865,12 @@ class AArch64Operand : public MCParsedAsmOperand {
VecListIdx_PReg = 3,
};

template <VecListIndexType RegTy, unsigned NumRegs>
template <VecListIndexType RegTy, unsigned NumRegs,
bool IsConsecutive = false>
void addVectorListOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
assert((!IsConsecutive || (getVectorListStride() == 1)) &&
"Expected consecutive registers");
static const unsigned FirstRegs[][5] = {
/* DReg */ { AArch64::Q0,
AArch64::D0, AArch64::D0_D1,
Expand Down
24 changes: 24 additions & 0 deletions llvm/test/MC/AArch64/neon-diagnostics.s
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Expand Up @@ -6914,6 +6914,9 @@
tbl v0.8b, {v1.8b, v2.8b, v3.8b}, v2.8b
tbl v0.8b, {v1.8b, v2.8b, v3.8b, v4.8b}, v2.8b
tbl v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b, v5.16b}, v2.8b
tbl v0.8b, {v2.16b, v4.16b, v6.16b, v8.16b}, v10.8b
tbl.8b v0, {v2, v4, v6, v8}, v10
tbl.16b v0, {v2, v4, v6, v8}, v10

// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: tbl v0.8b, {v1.8b}, v2.8b
Expand All @@ -6930,12 +6933,24 @@
// CHECK-ERROR: error: invalid number of vectors
// CHECK-ERROR: tbl v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b, v5.16b}, v2.8b
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: tbl v0.8b, {v2.16b, v4.16b, v6.16b, v8.16b}, v10.8b
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: tbl.8b v0, {v2, v4, v6, v8}, v10
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: tbl.16b v0, {v2, v4, v6, v8}, v10
// CHECK-ERROR: ^

tbx v0.8b, {v1.8b}, v2.8b
tbx v0.8b, {v1.8b, v2.8b}, v2.8b
tbx v0.8b, {v1.8b, v2.8b, v3.8b}, v2.8b
tbx v0.8b, {v1.8b, v2.8b, v3.8b, v4.8b}, v2.8b
tbx v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b, v5.16b}, v2.8b
tbx v0.8b, {v2.16b, v4.16b, v6.16b, v8.16b}, v10.8b
tbx.8b v0, {v2, v4, v6, v8}, v10
tbx.16b v0, {v2, v4, v6, v8}, v10

// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: tbx v0.8b, {v1.8b}, v2.8b
Expand All @@ -6952,6 +6967,15 @@
// CHECK-ERROR: error: invalid number of vectors
// CHECK-ERROR: tbx v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b, v5.16b}, v2.8b
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: tbx v0.8b, {v2.16b, v4.16b, v6.16b, v8.16b}, v10.8b
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: tbx.8b v0, {v2, v4, v6, v8}, v10
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: tbx.16b v0, {v2, v4, v6, v8}, v10
// CHECK-ERROR: ^

//----------------------------------------------------------------------
// Scalar Floating-point Convert To Lower Precision Narrow, Rounding To
Expand Down
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