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[RISCV] Check for register where immediate should be in RISCVInstrInfo::verifyInstruction. #120286

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Merged
merged 1 commit into from
Dec 17, 2024
Merged

[RISCV] Check for register where immediate should be in RISCVInstrInfo::verifyInstruction. #120286

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4 changes: 4 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2451,6 +2451,10 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
if (OpType >= RISCVOp::OPERAND_FIRST_RISCV_IMM &&
OpType <= RISCVOp::OPERAND_LAST_RISCV_IMM) {
const MachineOperand &MO = MI.getOperand(Index);
if (MO.isReg()) {
ErrInfo = "Expected a non-register operand.";
return false;
}
if (MO.isImm()) {
int64_t Imm = MO.getImm();
bool Ok;
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2 changes: 1 addition & 1 deletion llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
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Expand Up @@ -698,7 +698,7 @@ let Predicates = [HasVendorXCVmem, IsRV32], AddedComplexity = 1 in {
def : CVStriPat<post_store, CV_SW_ri_inc>;

def : CVStrriPat<post_truncsti8, CV_SB_rr_inc>;
def : CVStrriPat<post_truncsti16, CV_SH_ri_inc>;
def : CVStrriPat<post_truncsti16, CV_SH_rr_inc>;
def : CVStrriPat<post_store, CV_SW_rr_inc>;

def : CVStrrPat<truncstorei8, CV_SB_rr>;
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