[X86] Correct the cdisp8 encoding for VGF2P8AFFINEINVQB and VGF2P8AFFINEQB. #120340
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…INEQB. These instructions use a 64-bit broadcast size so the element size for CD8 should be 64.
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@llvm/pr-subscribers-mc @llvm/pr-subscribers-backend-x86 Author: Craig Topper (topperc) ChangesThese instructions use a 64-bit broadcast size so the element size for CD8 should be 64. Pointed out by larkmjc on discord. Full diff: https://github.com/llvm/llvm-project/pull/120340.diff 3 Files Affected:
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td
index 83a2e981ffd7a8..e899807cd1b7c5 100644
--- a/llvm/lib/Target/X86/X86InstrAVX512.td
+++ b/llvm/lib/Target/X86/X86InstrAVX512.td
@@ -12569,10 +12569,10 @@ multiclass GF2P8AFFINE_avx512_common<bits<8> Op, string OpStr, SDNode OpNode,
defm VGF2P8AFFINEINVQB : GF2P8AFFINE_avx512_common<0xCF, "vgf2p8affineinvqb",
X86GF2P8affineinvqb, SchedWriteVecIMul>,
- EVEX, VVVV, EVEX_CD8<8, CD8VF>, REX_W, AVX512AIi8Base;
+ EVEX, VVVV, EVEX_CD8<64, CD8VF>, REX_W, AVX512AIi8Base;
defm VGF2P8AFFINEQB : GF2P8AFFINE_avx512_common<0xCE, "vgf2p8affineqb",
X86GF2P8affineqb, SchedWriteVecIMul>,
- EVEX, VVVV, EVEX_CD8<8, CD8VF>, REX_W, AVX512AIi8Base;
+ EVEX, VVVV, EVEX_CD8<64, CD8VF>, REX_W, AVX512AIi8Base;
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/MC/X86/avx512gfni-att.s b/llvm/test/MC/X86/avx512gfni-att.s
index 975595deef58ea..1100b49aa444d4 100644
--- a/llvm/test/MC/X86/avx512gfni-att.s
+++ b/llvm/test/MC/X86/avx512gfni-att.s
@@ -176,3 +176,10 @@
// CHECK: encoding: [0x62,0xf3,0xdd,0x50,0xce,0x09,0x07]
vgf2p8affineqb $7, (%rcx){1to8}, %zmm20, %zmm1
+// CHECK: vgf2p8affineinvqb $7, 8(%rcx){1to8}, %zmm20, %zmm1
+// CHECK: encoding: [0x62,0xf3,0xdd,0x50,0xcf,0x49,0x01,0x07]
+ vgf2p8affineinvqb $7, 8(%rcx){1to8}, %zmm20, %zmm1
+
+// CHECK: vgf2p8affineqb $7, 8(%rcx){1to8}, %zmm20, %zmm1
+// CHECK: encoding: [0x62,0xf3,0xdd,0x50,0xce,0x49,0x01,0x07]
+ vgf2p8affineqb $7, 8(%rcx){1to8}, %zmm20, %zmm1
diff --git a/llvm/test/MC/X86/avx512vl_gfni-att.s b/llvm/test/MC/X86/avx512vl_gfni-att.s
index a44211332de601..33d7e45a7b32d2 100644
--- a/llvm/test/MC/X86/avx512vl_gfni-att.s
+++ b/llvm/test/MC/X86/avx512vl_gfni-att.s
@@ -352,3 +352,18 @@
// CHECK: encoding: [0x62,0xf3,0xdd,0x30,0xce,0x09,0x07]
vgf2p8affineqb $7, (%rcx){1to4}, %ymm20, %ymm1
+// CHECK: vgf2p8affineinvqb $7, 8(%rcx){1to2}, %xmm20, %xmm1
+// CHECK: encoding: [0x62,0xf3,0xdd,0x10,0xcf,0x49,0x01,0x07]
+ vgf2p8affineinvqb $7, 8(%rcx){1to2}, %xmm20, %xmm1
+
+// CHECK: vgf2p8affineinvqb $7, 8(%rcx){1to4}, %ymm20, %ymm1
+// CHECK: encoding: [0x62,0xf3,0xdd,0x30,0xcf,0x49,0x01,0x07]
+ vgf2p8affineinvqb $7, 8(%rcx){1to4}, %ymm20, %ymm1
+
+// CHECK: vgf2p8affineqb $7, 8(%rcx){1to2}, %xmm20, %xmm1
+// CHECK: encoding: [0x62,0xf3,0xdd,0x10,0xce,0x49,0x01,0x07]
+ vgf2p8affineqb $7, 8(%rcx){1to2}, %xmm20, %xmm1
+
+// CHECK: vgf2p8affineqb $7, 8(%rcx){1to4}, %ymm20, %ymm1
+// CHECK: encoding: [0x62,0xf3,0xdd,0x30,0xce,0x49,0x01,0x07]
+ vgf2p8affineqb $7, 8(%rcx){1to4}, %ymm20, %ymm1
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larkmjc here. I was performing some differential fuzzing and checking word size with the broadcast cdisp8 multiplier. just to add to the notes. here are my exemplars from before the patch along with binutils output. these differ slightly from the test cases as they are using SIB and the ib is 0 instead of 7. I have checked this patch on my side but haven't run the tests in the test suite yet. thanks. llvm (18:18.1.3-1ubuntu1)binutils (2.42-4ubuntu2.3) |
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/30/builds/12496 Here is the relevant piece of the build log for the reference |
KanRobert
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) during differential fuzzing, I found 8 more instructions with disp8 offset multiplier differences to binutils. somewhat sure there is a bug in the X86 LLVM disp8 offset multipliers for this subset of vector scatter and gather prefetch instructions. please check and refer to the previous pull request: #120340 these vector scatter and gather prefetch instructions also have an unusual k mask operand position but I have not addressed this with this patch as I am unsure how to change the Intel format in the tablegen file. ``` hex: 62 f2 fd 49 c6 4c 51 01 llvm: vgatherpf0dpd {k1}, zmmword ptr [rcx + 2*ymm2 + 4] ours: vgatherpf0dpd qword ptr * 8 [rcx + 2*ymm2 + 8] {k1} gnu: vgatherpf0dpd QWORD PTR [rcx+ymm2*2+0x8]{k1} hex: 62 f2 7d 49 c7 4c 51 01 llvm: vgatherpf0qps {k1}, ymmword ptr [rcx + 2*zmm2 + 8] ours: vgatherpf0qps dword ptr * 8 [rcx + 2*zmm2 + 4] {k1} gnu: vgatherpf0qps DWORD PTR [rcx+zmm2*2+0x4]{k1} hex: 62 f2 fd 49 c6 54 51 01 llvm: vgatherpf1dpd {k1}, zmmword ptr [rcx + 2*ymm2 + 4] ours: vgatherpf1dpd qword ptr * 8 [rcx + 2*ymm2 + 8] {k1} gnu: vgatherpf1dpd QWORD PTR [rcx+ymm2*2+0x8]{k1} hex: 62 f2 7d 49 c7 54 51 01 llvm: vgatherpf1qps {k1}, ymmword ptr [rcx + 2*zmm2 + 8] ours: vgatherpf1qps dword ptr * 8 [rcx + 2*zmm2 + 4] {k1} gnu: vgatherpf1qps DWORD PTR [rcx+zmm2*2+0x4]{k1} hex: 62 f2 fd 49 c6 6c 51 01 llvm: vscatterpf0dpd {k1}, zmmword ptr [rcx + 2*ymm2 + 4] ours: vscatterpf0dpd qword ptr * 8 [rcx + 2*ymm2 + 8] {k1} gnu: vscatterpf0dpd QWORD PTR [rcx+ymm2*2+0x8]{k1} hex: 62 f2 7d 49 c7 6c 51 01 llvm: vscatterpf0qps {k1}, ymmword ptr [rcx + 2*zmm2 + 8] ours: vscatterpf0qps dword ptr * 8 [rcx + 2*zmm2 + 4] {k1} gnu: vscatterpf0qps DWORD PTR [rcx+zmm2*2+0x4]{k1} hex: 62 f2 fd 49 c6 74 51 01 llvm: vscatterpf1dpd {k1}, zmmword ptr [rcx + 2*ymm2 + 4] ours: vscatterpf1dpd qword ptr * 8 [rcx + 2*ymm2 + 8] {k1} gnu: vscatterpf1dpd QWORD PTR [rcx+ymm2*2+0x8]{k1} hex: 62 f2 7d 49 c7 74 51 01 llvm: vscatterpf1qps {k1}, ymmword ptr [rcx + 2*zmm2 + 8] ours: vscatterpf1qps dword ptr * 8 [rcx + 2*zmm2 + 4] {k1} gnu: vscatterpf1qps DWORD PTR [rcx+zmm2*2+0x4]{k1} ```
github-actions bot
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…fetch (#122051) during differential fuzzing, I found 8 more instructions with disp8 offset multiplier differences to binutils. somewhat sure there is a bug in the X86 LLVM disp8 offset multipliers for this subset of vector scatter and gather prefetch instructions. please check and refer to the previous pull request: llvm/llvm-project#120340 these vector scatter and gather prefetch instructions also have an unusual k mask operand position but I have not addressed this with this patch as I am unsure how to change the Intel format in the tablegen file. ``` hex: 62 f2 fd 49 c6 4c 51 01 llvm: vgatherpf0dpd {k1}, zmmword ptr [rcx + 2*ymm2 + 4] ours: vgatherpf0dpd qword ptr * 8 [rcx + 2*ymm2 + 8] {k1} gnu: vgatherpf0dpd QWORD PTR [rcx+ymm2*2+0x8]{k1} hex: 62 f2 7d 49 c7 4c 51 01 llvm: vgatherpf0qps {k1}, ymmword ptr [rcx + 2*zmm2 + 8] ours: vgatherpf0qps dword ptr * 8 [rcx + 2*zmm2 + 4] {k1} gnu: vgatherpf0qps DWORD PTR [rcx+zmm2*2+0x4]{k1} hex: 62 f2 fd 49 c6 54 51 01 llvm: vgatherpf1dpd {k1}, zmmword ptr [rcx + 2*ymm2 + 4] ours: vgatherpf1dpd qword ptr * 8 [rcx + 2*ymm2 + 8] {k1} gnu: vgatherpf1dpd QWORD PTR [rcx+ymm2*2+0x8]{k1} hex: 62 f2 7d 49 c7 54 51 01 llvm: vgatherpf1qps {k1}, ymmword ptr [rcx + 2*zmm2 + 8] ours: vgatherpf1qps dword ptr * 8 [rcx + 2*zmm2 + 4] {k1} gnu: vgatherpf1qps DWORD PTR [rcx+zmm2*2+0x4]{k1} hex: 62 f2 fd 49 c6 6c 51 01 llvm: vscatterpf0dpd {k1}, zmmword ptr [rcx + 2*ymm2 + 4] ours: vscatterpf0dpd qword ptr * 8 [rcx + 2*ymm2 + 8] {k1} gnu: vscatterpf0dpd QWORD PTR [rcx+ymm2*2+0x8]{k1} hex: 62 f2 7d 49 c7 6c 51 01 llvm: vscatterpf0qps {k1}, ymmword ptr [rcx + 2*zmm2 + 8] ours: vscatterpf0qps dword ptr * 8 [rcx + 2*zmm2 + 4] {k1} gnu: vscatterpf0qps DWORD PTR [rcx+zmm2*2+0x4]{k1} hex: 62 f2 fd 49 c6 74 51 01 llvm: vscatterpf1dpd {k1}, zmmword ptr [rcx + 2*ymm2 + 4] ours: vscatterpf1dpd qword ptr * 8 [rcx + 2*ymm2 + 8] {k1} gnu: vscatterpf1dpd QWORD PTR [rcx+ymm2*2+0x8]{k1} hex: 62 f2 7d 49 c7 74 51 01 llvm: vscatterpf1qps {k1}, ymmword ptr [rcx + 2*zmm2 + 8] ours: vscatterpf1qps dword ptr * 8 [rcx + 2*zmm2 + 4] {k1} gnu: vscatterpf1qps DWORD PTR [rcx+zmm2*2+0x4]{k1} ```
BaiXilin
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Jan 12, 2025
…#122051) during differential fuzzing, I found 8 more instructions with disp8 offset multiplier differences to binutils. somewhat sure there is a bug in the X86 LLVM disp8 offset multipliers for this subset of vector scatter and gather prefetch instructions. please check and refer to the previous pull request: llvm#120340 these vector scatter and gather prefetch instructions also have an unusual k mask operand position but I have not addressed this with this patch as I am unsure how to change the Intel format in the tablegen file. ``` hex: 62 f2 fd 49 c6 4c 51 01 llvm: vgatherpf0dpd {k1}, zmmword ptr [rcx + 2*ymm2 + 4] ours: vgatherpf0dpd qword ptr * 8 [rcx + 2*ymm2 + 8] {k1} gnu: vgatherpf0dpd QWORD PTR [rcx+ymm2*2+0x8]{k1} hex: 62 f2 7d 49 c7 4c 51 01 llvm: vgatherpf0qps {k1}, ymmword ptr [rcx + 2*zmm2 + 8] ours: vgatherpf0qps dword ptr * 8 [rcx + 2*zmm2 + 4] {k1} gnu: vgatherpf0qps DWORD PTR [rcx+zmm2*2+0x4]{k1} hex: 62 f2 fd 49 c6 54 51 01 llvm: vgatherpf1dpd {k1}, zmmword ptr [rcx + 2*ymm2 + 4] ours: vgatherpf1dpd qword ptr * 8 [rcx + 2*ymm2 + 8] {k1} gnu: vgatherpf1dpd QWORD PTR [rcx+ymm2*2+0x8]{k1} hex: 62 f2 7d 49 c7 54 51 01 llvm: vgatherpf1qps {k1}, ymmword ptr [rcx + 2*zmm2 + 8] ours: vgatherpf1qps dword ptr * 8 [rcx + 2*zmm2 + 4] {k1} gnu: vgatherpf1qps DWORD PTR [rcx+zmm2*2+0x4]{k1} hex: 62 f2 fd 49 c6 6c 51 01 llvm: vscatterpf0dpd {k1}, zmmword ptr [rcx + 2*ymm2 + 4] ours: vscatterpf0dpd qword ptr * 8 [rcx + 2*ymm2 + 8] {k1} gnu: vscatterpf0dpd QWORD PTR [rcx+ymm2*2+0x8]{k1} hex: 62 f2 7d 49 c7 6c 51 01 llvm: vscatterpf0qps {k1}, ymmword ptr [rcx + 2*zmm2 + 8] ours: vscatterpf0qps dword ptr * 8 [rcx + 2*zmm2 + 4] {k1} gnu: vscatterpf0qps DWORD PTR [rcx+zmm2*2+0x4]{k1} hex: 62 f2 fd 49 c6 74 51 01 llvm: vscatterpf1dpd {k1}, zmmword ptr [rcx + 2*ymm2 + 4] ours: vscatterpf1dpd qword ptr * 8 [rcx + 2*ymm2 + 8] {k1} gnu: vscatterpf1dpd QWORD PTR [rcx+ymm2*2+0x8]{k1} hex: 62 f2 7d 49 c7 74 51 01 llvm: vscatterpf1qps {k1}, ymmword ptr [rcx + 2*zmm2 + 8] ours: vscatterpf1qps dword ptr * 8 [rcx + 2*zmm2 + 4] {k1} gnu: vscatterpf1qps DWORD PTR [rcx+zmm2*2+0x4]{k1} ```
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These instructions use a 64-bit broadcast size so the element size for CD8 should be 64.
Pointed out by larkmjc on discord.