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[AArch64] Enable FEAT_SVE2p1 by default for Armv9.4-A and later #120753

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Dec 20, 2024
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Original file line number Diff line number Diff line change
Expand Up @@ -58,6 +58,7 @@
// CHECK-NEXT: FEAT_SSBS, FEAT_SSBS2 Enable Speculative Store Bypass Safe bit
// CHECK-NEXT: FEAT_SVE Enable Scalable Vector Extension (SVE) instructions
// CHECK-NEXT: FEAT_SVE2 Enable Scalable Vector Extension 2 (SVE2) instructions
// CHECK-NEXT: FEAT_SVE2p1 Enable Scalable Vector Extension 2.1 instructions
// CHECK-NEXT: FEAT_TLBIOS, FEAT_TLBIRANGE Enable Armv8.4-A TLB Range and Maintenance instructions
// CHECK-NEXT: FEAT_TRBE Enable Trace Buffer Extension
// CHECK-NEXT: FEAT_TRF Enable Armv8.4-A Trace extension
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Original file line number Diff line number Diff line change
Expand Up @@ -61,6 +61,7 @@
// CHECK-NEXT: FEAT_SSBS, FEAT_SSBS2 Enable Speculative Store Bypass Safe bit
// CHECK-NEXT: FEAT_SVE Enable Scalable Vector Extension (SVE) instructions
// CHECK-NEXT: FEAT_SVE2 Enable Scalable Vector Extension 2 (SVE2) instructions
// CHECK-NEXT: FEAT_SVE2p1 Enable Scalable Vector Extension 2.1 instructions
// CHECK-NEXT: FEAT_TLBIOS, FEAT_TLBIRANGE Enable Armv8.4-A TLB Range and Maintenance instructions
// CHECK-NEXT: FEAT_TRBE Enable Trace Buffer Extension
// CHECK-NEXT: FEAT_TRF Enable Armv8.4-A Trace extension
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2 changes: 1 addition & 1 deletion llvm/lib/Target/AArch64/AArch64Features.td
Original file line number Diff line number Diff line change
Expand Up @@ -874,7 +874,7 @@ def HasV9_3aOps : Architecture64<9, 3, "a", "v9.3a",
def HasV9_4aOps : Architecture64<9, 4, "a", "v9.4a",
[HasV8_9aOps, HasV9_3aOps],
!listconcat(HasV9_3aOps.DefaultExts, [FeatureSPECRES2, FeatureCSSC,
FeatureRASv2])>;
FeatureRASv2, FeatureSVE2p1])>;
def HasV9_5aOps : Architecture64<9, 5, "a", "v9.5a",
[HasV9_4aOps, FeatureCPA],
!listconcat(HasV9_4aOps.DefaultExts, [FeatureCPA, FeatureLUT, FeatureFAMINMAX])>;
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