AMDGPU: Fix assert on physreg MUBUF rsrc operand

[arsenm]

The stack case uses a physical register and should not ordinarily
reach here, but strange things happen at -O0. The testcase still
errors because we do not yet attempt to handle arbitrary dynamic
sized allocas yet.

Fixes: SWDEV-503538

[arsenm]

• AMDGPU: Fix assert on physreg MUBUF rsrc operand #120815 👈 (View in Graphite)
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[llvmbot]

@llvm/pr-subscribers-backend-amdgpu

Author: Matt Arsenault (arsenm)

Changes

The stack case uses a physical register and should not ordinarily
reach here, but strange things happen at -O0. The testcase still
errors because we do not yet attempt to handle arbitrary dynamic
sized allocas yet.

Fixes: SWDEV-503538

---

Full diff: https://github.com/llvm/llvm-project/pull/120815.diff

2 Files Affected:

• (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.cpp (+1-2)
• (added) llvm/test/CodeGen/AMDGPU/swdev503538-move-to-valu-stack-srd-physreg.ll (+23)

diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index f97ea40caa6704..7e61aa9cd1da6a 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -6866,9 +6866,8 @@ SIInstrInfo::legalizeOperands(MachineInstr &MI,
       AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc);
   if (RsrcIdx != -1) {
     MachineOperand *Rsrc = &MI.getOperand(RsrcIdx);
-    if (Rsrc->isReg() && !RI.isSGPRClass(MRI.getRegClass(Rsrc->getReg()))) {
+    if (Rsrc->isReg() && !RI.isSGPRReg(MRI, Rsrc->getReg()))
       isRsrcLegal = false;
-    }
   }
 
   // The operands are legal.
diff --git a/llvm/test/CodeGen/AMDGPU/swdev503538-move-to-valu-stack-srd-physreg.ll b/llvm/test/CodeGen/AMDGPU/swdev503538-move-to-valu-stack-srd-physreg.ll
new file mode 100644
index 00000000000000..6849c8b4e609ee
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/swdev503538-move-to-valu-stack-srd-physreg.ll
@@ -0,0 +1,23 @@
+; RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -O0 2> %t.err < %s | FileCheck %s
+; RUN: FileCheck -check-prefix=ERR %s < %t.err
+
+; FIXME: This error will be fixed by supporting arbitrary divergent
+; dynamic allocas by performing a wave umax of the size.
+
+; ERR: error: <unknown>:0:0: in function move_to_valu_assert_srd_is_physreg_swdev503538 i32 (ptr addrspace(1)): illegal VGPR to SGPR copy
+
+; CHECK: ; illegal copy v0 to s32
+
+define i32 @move_to_valu_assert_srd_is_physreg_swdev503538(ptr addrspace(1) %ptr) {
+entry:
+  %idx = load i32, ptr addrspace(1) %ptr, align 4
+  %zero = extractelement <4 x i32> zeroinitializer, i32 %idx
+  %alloca = alloca [2048 x i8], i32 %zero, align 8, addrspace(5)
+  %ld = load i32, ptr addrspace(5) %alloca, align 8
+  call void @llvm.memset.p5.i32(ptr addrspace(5) %alloca, i8 0, i32 2048, i1 false)
+  ret i32 %ld
+}
+
+declare void @llvm.memset.p5.i32(ptr addrspace(5) nocapture writeonly, i8, i32, i1 immarg) #0
+
+attributes #0 = { nocallback nofree nounwind willreturn memory(argmem: write) }

[mikaelholmen]

Not sure what happens but I see that
llvm/CodeGen/AMDGPU/swdev503538-move-to-valu-stack-srd-physreg.ll
fails if I run it when I've compiled with EXPENSIVE_CHECKS

-> build-all-expensive/bin/llvm-lit -av test/CodeGen/AMDGPU/swdev503538-move-to-valu-stack-srd-physreg.ll                                                                                  -- Testing: 1 tests, 1 workers --
FAIL: LLVM :: CodeGen/AMDGPU/swdev503538-move-to-valu-stack-srd-physreg.ll (1 of 1)
******************** TEST 'LLVM :: CodeGen/AMDGPU/swdev503538-move-to-valu-stack-srd-physreg.ll' FAILED ********************
Exit Code: 2

Command Output (stderr):
--
RUN: at line 1: not /repo/llvm/build-all-expensive/bin/llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -O0 2> /repo/llvm/build-all-expensive/test/CodeGen/AMDGPU/Output/swdev503538-move-to-valu-stack-srd-physreg.ll.tmp.err < /repo/llvm/test/CodeGen/AMDGPU/swdev503538-move-to-valu-stack-srd-physreg.ll | /repo/llvm/build-all-expensive/bin/FileCheck /repo/llvm/test/CodeGen/AMDGPU/swdev503538-move-to-valu-stack-srd-physreg.ll
+ /repo/llvm/build-all-expensive/bin/FileCheck /repo/llvm/test/CodeGen/AMDGPU/swdev503538-move-to-valu-stack-srd-physreg.ll
+ not /repo/llvm/build-all-expensive/bin/llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -O0
FileCheck error: '<stdin>' is empty.
FileCheck command line:  /repo/llvm/build-all-expensive/bin/FileCheck /repo/llvm/test/CodeGen/AMDGPU/swdev503538-move-to-valu-stack-srd-physreg.ll

--

********************
********************
Failed Tests (1):
  LLVM :: CodeGen/AMDGPU/swdev503538-move-to-valu-stack-srd-physreg.ll

[arsenm]

Not sure what happens but I see that llvm/CodeGen/AMDGPU/swdev503538-move-to-valu-stack-srd-physreg.ll fails if I run it when I've compiled with EXPENSIVE_CHECKS

This test needs to explicitly disable the verifier since it's broken

[arsenm]

This test needs to explicitly disable the verifier since it's broken

Done in 7899572

[mikaelholmen]

This test needs to explicitly disable the verifier since it's broken

Done in 7899572

Thanks