[TableGen][GlobalISel] Add GINodeEquiv for sdivrem/udivrem

[s-barannikov]

These nodes are not currently used in DAG patterns. Their GlobalISel equivalents are primarily useful for testing TableGen backend, as they produce two results. (There doesn't seem to be other such nodes.)

[llvmbot]

@llvm/pr-subscribers-llvm-selectiondag

@llvm/pr-subscribers-llvm-globalisel

Author: Sergei Barannikov (s-barannikov)

Changes

These nodes are not currently used in DAG patterns. Their GlobalISel equivalents are primarily useful for testing TableGen backend, as they produce two results. (There doesn't seem to be other such nodes.)

---

Full diff: https://github.com/llvm/llvm-project/pull/120819.diff

2 Files Affected:

• (modified) llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td (+2)
• (modified) llvm/include/llvm/Target/TargetSelectionDAG.td (+2-2)

diff --git a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
index 2148f5be4c41aa..c8c0eeb57099a2 100644
--- a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
+++ b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
@@ -70,6 +70,8 @@ def : GINodeEquiv<G_SDIV, sdiv>;
 def : GINodeEquiv<G_UDIV, udiv>;
 def : GINodeEquiv<G_SREM, srem>;
 def : GINodeEquiv<G_UREM, urem>;
+def : GINodeEquiv<G_SDIVREM, sdivrem>;
+def : GINodeEquiv<G_UDIVREM, udivrem>;
 def : GINodeEquiv<G_AND, and>;
 def : GINodeEquiv<G_OR, or>;
 def : GINodeEquiv<G_XOR, xor>;
diff --git a/llvm/include/llvm/Target/TargetSelectionDAG.td b/llvm/include/llvm/Target/TargetSelectionDAG.td
index 2c58eedce1de0b..bee0a4298c786f 100644
--- a/llvm/include/llvm/Target/TargetSelectionDAG.td
+++ b/llvm/include/llvm/Target/TargetSelectionDAG.td
@@ -128,8 +128,8 @@ def SDTIntShiftDOp: SDTypeProfile<1, 3, [   // fshl, fshr
 def SDTIntSatNoShOp : SDTypeProfile<1, 2, [   // ssat with no shift
   SDTCisSameAs<0, 1>, SDTCisInt<2>
 ]>;
-def SDTIntBinHiLoOp : SDTypeProfile<2, 2, [ // mulhi, mullo, sdivrem, udivrem
-  SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,SDTCisInt<0>
+def SDTIntBinHiLoOp : SDTypeProfile<2, 2, [ // smullohi, umullohi, sdivrem, udivrem
+  SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisInt<0>
 ]>;
 def SDTIntScaledBinOp : SDTypeProfile<1, 3, [  // smulfix, sdivfix, etc
   SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisInt<3>

[arsenm]

But you can't select nodes with multiple outputs in tablegen. There's no syntax to match it

[s-barannikov]

But you can't select nodes with multiple outputs in tablegen. There's no syntax to match it

I think I can? Something like this:
(set GPR32:$rd1, GPR32:$rd2, (sdivrem i32:$rs1, i32:$rs2))
or
def : Pat<(sdivrem i32:$lhs, i32:$rhs), (MY_SDIVREM $lhs, $rhs)>;
(assuming MY_SDIVREM has two explicit defs).