[NVPTX] Remove redundant types from TableGen patterns (NFC) #120986
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@llvm/pr-subscribers-backend-nvptx Author: Alex MacLean (AlexMaclean) ChangesThese types in the output dag of a Pat do not impact the generated matcher code at all. Removing them makes for more concise and readable code. Patch is 76.34 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/120986.diff 2 Files Affected:
diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
index 711cd67eceed9a5..c3e72d6ce3a3f8f 100644
--- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
+++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
@@ -733,12 +733,12 @@ def fpround_oneuse : PatFrag<(ops node:$a), (fpround node:$a), [{
def : Pat<(v2bf16 (build_vector (bf16 (fpround_oneuse f32:$lo)),
(bf16 (fpround_oneuse f32:$hi)))),
- (CVT_bf16x2_f32 Float32Regs:$hi, Float32Regs:$lo, CvtRN)>,
+ (CVT_bf16x2_f32 $hi, $lo, CvtRN)>,
Requires<[hasPTX<70>, hasSM<80>, hasBF16Math]>;
def : Pat<(v2f16 (build_vector (f16 (fpround_oneuse f32:$lo)),
(f16 (fpround_oneuse f32:$hi)))),
- (CVT_f16x2_f32 Float32Regs:$hi, Float32Regs:$lo, CvtRN)>,
+ (CVT_f16x2_f32 $hi, $lo, CvtRN)>,
Requires<[hasPTX<70>, hasSM<80>, useFP16Math]>;
//-----------------------------------
@@ -813,7 +813,7 @@ defm SELP_f64 : SELP_PATTERN<"f64", f64, Float64Regs, f64imm, fpimm>;
foreach vt = [v2f16, v2bf16, v2i16, v4i8] in {
def : Pat<(vt (select i1:$p, vt:$a, vt:$b)),
- (SELP_b32rr Int32Regs:$a, Int32Regs:$b, Int1Regs:$p)>;
+ (SELP_b32rr $a, $b, $p)>;
}
//-----------------------------------
@@ -952,29 +952,29 @@ def mul_wide_unsigned : SDNode<"NVPTXISD::MUL_WIDE_UNSIGNED", SDTMulWide>;
// Matchers for signed, unsigned mul.wide ISD nodes.
def : Pat<(i32 (mul_wide_signed i16:$a, i16:$b)),
- (MULWIDES32 i16:$a, i16:$b)>,
+ (MULWIDES32 $a, $b)>,
Requires<[doMulWide]>;
def : Pat<(i32 (mul_wide_signed i16:$a, imm:$b)),
- (MULWIDES32Imm Int16Regs:$a, imm:$b)>,
+ (MULWIDES32Imm $a, imm:$b)>,
Requires<[doMulWide]>;
def : Pat<(i32 (mul_wide_unsigned i16:$a, i16:$b)),
- (MULWIDEU32 Int16Regs:$a, Int16Regs:$b)>,
+ (MULWIDEU32 $a, $b)>,
Requires<[doMulWide]>;
def : Pat<(i32 (mul_wide_unsigned i16:$a, imm:$b)),
- (MULWIDEU32Imm Int16Regs:$a, imm:$b)>,
+ (MULWIDEU32Imm $a, imm:$b)>,
Requires<[doMulWide]>;
def : Pat<(i64 (mul_wide_signed i32:$a, i32:$b)),
- (MULWIDES64 Int32Regs:$a, Int32Regs:$b)>,
+ (MULWIDES64 $a, $b)>,
Requires<[doMulWide]>;
def : Pat<(i64 (mul_wide_signed i32:$a, imm:$b)),
- (MULWIDES64Imm Int32Regs:$a, imm:$b)>,
+ (MULWIDES64Imm $a, imm:$b)>,
Requires<[doMulWide]>;
def : Pat<(i64 (mul_wide_unsigned i32:$a, i32:$b)),
- (MULWIDEU64 Int32Regs:$a, Int32Regs:$b)>,
+ (MULWIDEU64 $a, $b)>,
Requires<[doMulWide]>;
def : Pat<(i64 (mul_wide_unsigned i32:$a, imm:$b)),
- (MULWIDEU64Imm Int32Regs:$a, imm:$b)>,
+ (MULWIDEU64Imm $a, imm:$b)>,
Requires<[doMulWide]>;
// Predicates used for converting some patterns to mul.wide.
@@ -1024,46 +1024,46 @@ def SHL2MUL16 : SDNodeXForm<imm, [{
// Convert "sign/zero-extend, then shift left by an immediate" to mul.wide.
def : Pat<(shl (sext i32:$a), (i32 IntConst_0_30:$b)),
- (MULWIDES64Imm Int32Regs:$a, (SHL2MUL32 node:$b))>,
+ (MULWIDES64Imm $a, (SHL2MUL32 $b))>,
Requires<[doMulWide]>;
def : Pat<(shl (zext i32:$a), (i32 IntConst_0_30:$b)),
- (MULWIDEU64Imm Int32Regs:$a, (SHL2MUL32 node:$b))>,
+ (MULWIDEU64Imm $a, (SHL2MUL32 $b))>,
Requires<[doMulWide]>;
def : Pat<(shl (sext i16:$a), (i16 IntConst_0_14:$b)),
- (MULWIDES32Imm Int16Regs:$a, (SHL2MUL16 node:$b))>,
+ (MULWIDES32Imm $a, (SHL2MUL16 $b))>,
Requires<[doMulWide]>;
def : Pat<(shl (zext i16:$a), (i16 IntConst_0_14:$b)),
- (MULWIDEU32Imm Int16Regs:$a, (SHL2MUL16 node:$b))>,
+ (MULWIDEU32Imm $a, (SHL2MUL16 $b))>,
Requires<[doMulWide]>;
// Convert "sign/zero-extend then multiply" to mul.wide.
def : Pat<(mul (sext i32:$a), (sext i32:$b)),
- (MULWIDES64 Int32Regs:$a, Int32Regs:$b)>,
+ (MULWIDES64 $a, $b)>,
Requires<[doMulWide]>;
def : Pat<(mul (sext i32:$a), (i64 SInt32Const:$b)),
- (MULWIDES64Imm64 Int32Regs:$a, (i64 SInt32Const:$b))>,
+ (MULWIDES64Imm64 $a, (i64 SInt32Const:$b))>,
Requires<[doMulWide]>;
def : Pat<(mul (zext i32:$a), (zext i32:$b)),
- (MULWIDEU64 Int32Regs:$a, Int32Regs:$b)>,
+ (MULWIDEU64 $a, $b)>,
Requires<[doMulWide]>;
def : Pat<(mul (zext i32:$a), (i64 UInt32Const:$b)),
- (MULWIDEU64Imm64 Int32Regs:$a, (i64 UInt32Const:$b))>,
+ (MULWIDEU64Imm64 $a, (i64 UInt32Const:$b))>,
Requires<[doMulWide]>;
def : Pat<(mul (sext i16:$a), (sext i16:$b)),
- (MULWIDES32 Int16Regs:$a, Int16Regs:$b)>,
+ (MULWIDES32 $a, $b)>,
Requires<[doMulWide]>;
def : Pat<(mul (sext i16:$a), (i32 SInt16Const:$b)),
- (MULWIDES32Imm32 Int16Regs:$a, (i32 SInt16Const:$b))>,
+ (MULWIDES32Imm32 $a, (i32 SInt16Const:$b))>,
Requires<[doMulWide]>;
def : Pat<(mul (zext i16:$a), (zext i16:$b)),
- (MULWIDEU32 Int16Regs:$a, Int16Regs:$b)>,
+ (MULWIDEU32 $a, $b)>,
Requires<[doMulWide]>;
def : Pat<(mul (zext i16:$a), (i32 UInt16Const:$b)),
- (MULWIDEU32Imm32 Int16Regs:$a, (i32 UInt16Const:$b))>,
+ (MULWIDEU32Imm32 $a, (i32 UInt16Const:$b))>,
Requires<[doMulWide]>;
//
@@ -1242,7 +1242,7 @@ def FDIV64ri :
// fdiv will be converted to rcp
// fneg (fdiv 1.0, X) => fneg (rcp.rn X)
def : Pat<(fdiv DoubleConstNeg1:$a, f64:$b),
- (FNEGf64 (FDIV641r (NegDoubleConst node:$a), Float64Regs:$b))>;
+ (FNEGf64 (FDIV641r (NegDoubleConst node:$a), $b))>;
//
// F32 Approximate reciprocal
@@ -1436,83 +1436,83 @@ def COSF: NVPTXInst<(outs Float32Regs:$dst), (ins Float32Regs:$src),
// frem - f32 FTZ
def : Pat<(frem f32:$x, f32:$y),
- (FSUBf32rr_ftz Float32Regs:$x, (FMULf32rr_ftz (CVT_f32_f32
- (FDIV32rr_prec_ftz Float32Regs:$x, Float32Regs:$y), CvtRZI_FTZ),
- Float32Regs:$y))>,
+ (FSUBf32rr_ftz $x, (FMULf32rr_ftz (CVT_f32_f32
+ (FDIV32rr_prec_ftz $x, $y), CvtRZI_FTZ),
+ $y))>,
Requires<[doF32FTZ, allowUnsafeFPMath]>;
def : Pat<(frem f32:$x, fpimm:$y),
- (FSUBf32rr_ftz Float32Regs:$x, (FMULf32ri_ftz (CVT_f32_f32
- (FDIV32ri_prec_ftz Float32Regs:$x, fpimm:$y), CvtRZI_FTZ),
+ (FSUBf32rr_ftz $x, (FMULf32ri_ftz (CVT_f32_f32
+ (FDIV32ri_prec_ftz $x, fpimm:$y), CvtRZI_FTZ),
fpimm:$y))>,
Requires<[doF32FTZ, allowUnsafeFPMath]>;
-def : Pat<(frem f32:$x, Float32Regs:$y),
- (SELP_f32rr Float32Regs:$x,
- (FSUBf32rr_ftz Float32Regs:$x, (FMULf32rr_ftz (CVT_f32_f32
- (FDIV32rr_prec_ftz Float32Regs:$x, Float32Regs:$y), CvtRZI_FTZ),
- Float32Regs:$y)),
- (TESTINF_f32r Float32Regs:$y))>,
+def : Pat<(frem f32:$x, f32:$y),
+ (SELP_f32rr $x,
+ (FSUBf32rr_ftz $x, (FMULf32rr_ftz (CVT_f32_f32
+ (FDIV32rr_prec_ftz $x, $y), CvtRZI_FTZ),
+ $y)),
+ (TESTINF_f32r $y))>,
Requires<[doF32FTZ, noUnsafeFPMath]>;
def : Pat<(frem f32:$x, fpimm:$y),
- (SELP_f32rr Float32Regs:$x,
- (FSUBf32rr_ftz Float32Regs:$x, (FMULf32ri_ftz (CVT_f32_f32
- (FDIV32ri_prec_ftz Float32Regs:$x, fpimm:$y), CvtRZI_FTZ),
+ (SELP_f32rr $x,
+ (FSUBf32rr_ftz $x, (FMULf32ri_ftz (CVT_f32_f32
+ (FDIV32ri_prec_ftz $x, fpimm:$y), CvtRZI_FTZ),
fpimm:$y)),
(TESTINF_f32i fpimm:$y))>,
Requires<[doF32FTZ, noUnsafeFPMath]>;
// frem - f32
def : Pat<(frem f32:$x, f32:$y),
- (FSUBf32rr Float32Regs:$x, (FMULf32rr (CVT_f32_f32
- (FDIV32rr_prec Float32Regs:$x, Float32Regs:$y), CvtRZI),
- Float32Regs:$y))>,
+ (FSUBf32rr $x, (FMULf32rr (CVT_f32_f32
+ (FDIV32rr_prec $x, $y), CvtRZI),
+ $y))>,
Requires<[allowUnsafeFPMath]>;
def : Pat<(frem f32:$x, fpimm:$y),
- (FSUBf32rr Float32Regs:$x, (FMULf32ri (CVT_f32_f32
- (FDIV32ri_prec Float32Regs:$x, fpimm:$y), CvtRZI),
+ (FSUBf32rr $x, (FMULf32ri (CVT_f32_f32
+ (FDIV32ri_prec $x, fpimm:$y), CvtRZI),
fpimm:$y))>,
Requires<[allowUnsafeFPMath]>;
def : Pat<(frem f32:$x, f32:$y),
- (SELP_f32rr Float32Regs:$x,
- (FSUBf32rr Float32Regs:$x, (FMULf32rr (CVT_f32_f32
- (FDIV32rr_prec Float32Regs:$x, Float32Regs:$y), CvtRZI),
- Float32Regs:$y)),
+ (SELP_f32rr $x,
+ (FSUBf32rr $x, (FMULf32rr (CVT_f32_f32
+ (FDIV32rr_prec $x, $y), CvtRZI),
+ $y)),
(TESTINF_f32r Float32Regs:$y))>,
Requires<[noUnsafeFPMath]>;
def : Pat<(frem f32:$x, fpimm:$y),
- (SELP_f32rr Float32Regs:$x,
- (FSUBf32rr Float32Regs:$x, (FMULf32ri (CVT_f32_f32
- (FDIV32ri_prec Float32Regs:$x, fpimm:$y), CvtRZI),
+ (SELP_f32rr $x,
+ (FSUBf32rr $x, (FMULf32ri (CVT_f32_f32
+ (FDIV32ri_prec $x, fpimm:$y), CvtRZI),
fpimm:$y)),
(TESTINF_f32i fpimm:$y))>,
Requires<[noUnsafeFPMath]>;
// frem - f64
def : Pat<(frem f64:$x, f64:$y),
- (FSUBf64rr Float64Regs:$x, (FMULf64rr (CVT_f64_f64
- (FDIV64rr Float64Regs:$x, Float64Regs:$y), CvtRZI),
- Float64Regs:$y))>,
+ (FSUBf64rr $x, (FMULf64rr (CVT_f64_f64
+ (FDIV64rr $x, $y), CvtRZI),
+ $y))>,
Requires<[allowUnsafeFPMath]>;
def : Pat<(frem f64:$x, fpimm:$y),
- (FSUBf64rr Float64Regs:$x, (FMULf64ri (CVT_f64_f64
- (FDIV64ri Float64Regs:$x, fpimm:$y), CvtRZI),
+ (FSUBf64rr $x, (FMULf64ri (CVT_f64_f64
+ (FDIV64ri $x, fpimm:$y), CvtRZI),
fpimm:$y))>,
Requires<[allowUnsafeFPMath]>;
def : Pat<(frem f64:$x, f64:$y),
- (SELP_f64rr Float64Regs:$x,
- (FSUBf64rr Float64Regs:$x, (FMULf64rr (CVT_f64_f64
- (FDIV64rr Float64Regs:$x, Float64Regs:$y), CvtRZI),
- Float64Regs:$y)),
+ (SELP_f64rr $x,
+ (FSUBf64rr $x, (FMULf64rr (CVT_f64_f64
+ (FDIV64rr $x, $y), CvtRZI),
+ $y)),
(TESTINF_f64r Float64Regs:$y))>,
Requires<[noUnsafeFPMath]>;
def : Pat<(frem f64:$x, fpimm:$y),
- (SELP_f64rr Float64Regs:$x,
- (FSUBf64rr Float64Regs:$x, (FMULf64ri (CVT_f64_f64
- (FDIV64ri Float64Regs:$x, fpimm:$y), CvtRZI),
+ (SELP_f64rr $x,
+ (FSUBf64rr $x, (FMULf64ri (CVT_f64_f64
+ (FDIV64ri $x, fpimm:$y), CvtRZI),
fpimm:$y)),
- (TESTINF_f64r Float64Regs:$y))>,
+ (TESTINF_f64r $y))>,
Requires<[noUnsafeFPMath]>;
//-----------------------------------
@@ -1561,32 +1561,32 @@ defm AND : BITWISE<"and", and>;
defm XOR : BITWISE<"xor", xor>;
// PTX does not support mul on predicates, convert to and instructions
-def : Pat<(mul i1:$a, i1:$b), (ANDb1rr Int1Regs:$a, Int1Regs:$b)>;
-def : Pat<(mul i1:$a, imm:$b), (ANDb1ri Int1Regs:$a, imm:$b)>;
+def : Pat<(mul i1:$a, i1:$b), (ANDb1rr $a, $b)>;
+def : Pat<(mul i1:$a, imm:$b), (ANDb1ri $a, imm:$b)>;
// These transformations were once reliably performed by instcombine, but thanks
// to poison semantics they are no longer safe for LLVM IR, perform them here
// instead.
-def : Pat<(select i1:$a, i1:$b, 0), (ANDb1rr Int1Regs:$a, Int1Regs:$b)>;
-def : Pat<(select i1:$a, 1, i1:$b), (ORb1rr Int1Regs:$a, Int1Regs:$b)>;
+def : Pat<(select i1:$a, i1:$b, 0), (ANDb1rr $a, $b)>;
+def : Pat<(select i1:$a, 1, i1:$b), (ORb1rr $a, $b)>;
// Lower logical v2i16/v4i8 ops as bitwise ops on b32.
foreach vt = [v2i16, v4i8] in {
def: Pat<(or vt:$a, vt:$b),
- (ORb32rr Int32Regs:$a, Int32Regs:$b)>;
+ (ORb32rr $a, $b)>;
def: Pat<(xor vt:$a, vt:$b),
- (XORb32rr Int32Regs:$a, Int32Regs:$b)>;
+ (XORb32rr $a, $b)>;
def: Pat<(and vt:$a, vt:$b),
- (ANDb32rr Int32Regs:$a, Int32Regs:$b)>;
+ (ANDb32rr $a, $b)>;
// The constants get legalized into a bitcast from i32, so that's what we need
// to match here.
def: Pat<(or vt:$a, (vt (bitconvert (i32 imm:$b)))),
- (ORb32ri Int32Regs:$a, imm:$b)>;
+ (ORb32ri $a, imm:$b)>;
def: Pat<(xor vt:$a, (vt (bitconvert (i32 imm:$b)))),
- (XORb32ri Int32Regs:$a, imm:$b)>;
+ (XORb32ri $a, imm:$b)>;
def: Pat<(and vt:$a, (vt (bitconvert (i32 imm:$b)))),
- (ANDb32ri Int32Regs:$a, imm:$b)>;
+ (ANDb32ri $a, imm:$b)>;
}
def NOT1 : NVPTXInst<(outs Int1Regs:$dst), (ins Int1Regs:$src),
@@ -1770,34 +1770,34 @@ let hasSideEffects = false in {
// byte extraction + signed/unsigned extension to i32.
def : Pat<(i32 (sext_inreg (bfe i32:$s, i32:$o, 8), i8)),
- (BFE_S32rri Int32Regs:$s, Int32Regs:$o, 8)>;
+ (BFE_S32rri $s, $o, 8)>;
def : Pat<(i32 (sext_inreg (bfe i32:$s, imm:$o, 8), i8)),
- (BFE_S32rii Int32Regs:$s, imm:$o, 8)>;
+ (BFE_S32rii $s, imm:$o, 8)>;
def : Pat<(i32 (and (bfe i32:$s, i32:$o, 8), 255)),
- (BFE_U32rri Int32Regs:$s, Int32Regs:$o, 8)>;
+ (BFE_U32rri $s, $o, 8)>;
def : Pat<(i32 (and (bfe i32:$s, imm:$o, 8), 255)),
- (BFE_U32rii Int32Regs:$s, imm:$o, 8)>;
+ (BFE_U32rii $s, imm:$o, 8)>;
// byte extraction + signed extension to i16
def : Pat<(i16 (sext_inreg (trunc (bfe i32:$s, imm:$o, 8)), i8)),
- (CVT_s8_s32 (BFE_S32rii i32:$s, imm:$o, 8), CvtNONE)>;
+ (CVT_s8_s32 (BFE_S32rii $s, imm:$o, 8), CvtNONE)>;
// Byte extraction via shift/trunc/sext
def : Pat<(i16 (sext_inreg (trunc i32:$s), i8)),
- (CVT_s8_s32 Int32Regs:$s, CvtNONE)>;
+ (CVT_s8_s32 $s, CvtNONE)>;
def : Pat<(i16 (sext_inreg (trunc (srl i32:$s, (i32 imm:$o))), i8)),
- (CVT_s8_s32 (BFE_S32rii Int32Regs:$s, imm:$o, 8), CvtNONE)>;
+ (CVT_s8_s32 (BFE_S32rii $s, imm:$o, 8), CvtNONE)>;
def : Pat<(sext_inreg (srl i32:$s, (i32 imm:$o)), i8),
- (BFE_S32rii Int32Regs:$s, imm:$o, 8)>;
+ (BFE_S32rii $s, imm:$o, 8)>;
def : Pat<(i16 (sra (i16 (trunc i32:$s)), (i32 8))),
- (CVT_s8_s32 (BFE_S32rii Int32Regs:$s, 8, 8), CvtNONE)>;
+ (CVT_s8_s32 (BFE_S32rii $s, 8, 8), CvtNONE)>;
def : Pat<(sext_inreg (srl i64:$s, (i32 imm:$o)), i8),
- (BFE_S64rii Int64Regs:$s, imm:$o, 8)>;
+ (BFE_S64rii $s, imm:$o, 8)>;
def : Pat<(i16 (sext_inreg (trunc i64:$s), i8)),
- (CVT_s8_s64 Int64Regs:$s, CvtNONE)>;
+ (CVT_s8_s64 $s, CvtNONE)>;
def : Pat<(i16 (sext_inreg (trunc (srl i64:$s, (i32 imm:$o))), i8)),
- (CVT_s8_s64 (BFE_S64rii Int64Regs:$s, imm:$o, 8), CvtNONE)>;
+ (CVT_s8_s64 (BFE_S64rii $s, imm:$o, 8), CvtNONE)>;
//-----------------------------------
// Comparison instructions (setp, set)
@@ -2032,47 +2032,47 @@ multiclass ISET_FORMAT<PatFrag OpNode, PatLeaf Mode,
Instruction set_64ir> {
// i16 -> pred
def : Pat<(i1 (OpNode i16:$a, i16:$b)),
- (setp_16rr Int16Regs:$a, Int16Regs:$b, Mode)>;
+ (setp_16rr $a, $b, Mode)>;
def : Pat<(i1 (OpNode i16:$a, imm:$b)),
- (setp_16ri Int16Regs:$a, imm:$b, Mode)>;
+ (setp_16ri $a, imm:$b, Mode)>;
def : Pat<(i1 (OpNode imm:$a, i16:$b)),
- (setp_16ir imm:$a, Int16Regs:$b, Mode)>;
+ (setp_16ir imm:$a, $b, Mode)>;
// i32 -> pred
def : Pat<(i1 (OpNode i32:$a, i32:$b)),
- (setp_32rr Int32Regs:$a, Int32Regs:$b, Mode)>;
+ (setp_32rr $a, $b, Mode)>;
def : Pat<(i1 (OpNode i32:$a, imm:$b)),
- (setp_32ri Int32Regs:$a, imm:$b, Mode)>;
+ (setp_32ri $a, imm:$b, Mode)>;
def : Pat<(i1 (OpNode imm:$a, i32:$b)),
- (setp_32ir imm:$a, Int32Regs:$b, Mode)>;
+ (setp_32ir imm:$a, $b, Mode)>;
// i64 -> pred
def : Pat<(i1 (OpNode i64:$a, i64:$b)),
- (setp_64rr Int64Regs:$a, Int64Regs:$b, Mode)>;
+ (setp_64rr $a, $b, Mode)>;
def : Pat<(i1 (OpNode i64:$a, imm:$b)),
- (setp_64ri Int64Regs:$a, imm:$b, Mode)>;
+ (setp_64ri $a, imm:$b, Mode)>;
def : Pat<(i1 (OpNode imm:$a, i64:$b)),
- (setp_64ir imm:$a, Int64Regs:$b, Mode)>;
+ (setp_64ir imm:$a, $b, Mode)>;
// i16 -> i32
def : Pat<(i32 (OpNode i16:$a, i16:$b)),
- (set_16rr Int16Regs:$a, Int16Regs:$b, Mode)>;
+ (set_16rr $a, $b, Mode)>;
def : Pat<(i32 (OpNode i16:$a, imm:$b)),
- (set_16ri Int16Regs:$a, imm:$b, Mode)>;
+ (set_16ri $a, imm:$b, Mode)>;
def : Pat<(i32 (OpNode imm:$a, i16:$b)),
- (set_16ir imm:$a, Int16Regs:$b, Mode)>;
+ (set_16ir imm:$a, $b, Mode)>;
// i32 -> i32
def : Pat<(i32 (OpNode i32:$a, i32:$b)),
- (set_32rr Int32Regs:$a, Int32Regs:$b, Mode)>;
+ (set_32rr $a, $b, Mode)>;
def : Pat<(i32 (OpNode i32:$a, imm:$b)),
- (set_32ri Int32Regs:$a, imm:$b, Mode)>;
+ (set_32ri $a, imm:$b, Mode)>;
def : Pat<(i32 (OpNode imm:$a, i32:$b)),
- (set_32ir imm:$a, Int32Regs:$b, Mode)>;
+ (set_32ir imm:$a, $b, Mode)>;
// i64 -> i32
def : Pat<(i32 (OpNode i64:$a, Int64Regs:$b)),
- (set_64rr Int64Regs:$a, Int64Regs:$b, Mode)>;
+ (set_64rr $a, $b, Mode)>;
def : Pat<(i32 (OpNode i64:$a, imm:$b)),
- (set_64ri Int64Regs:$a, imm:$b, Mode)>;
+ (set_64ri $a, imm:$b, Mode)>;
def : Pat<(i32 (OpNode imm:$a, i64:$b)),
- (set_64ir imm:$a, Int64Regs:$b, Mode)>;
+ (set_64ir imm:$a, $b, Mode)>;
}
multiclass ISET_FORMAT_SIGNED<PatFrag OpNode, PatLeaf Mode>
@@ -2179,94 +2179,94 @@ def: Pat<(setne (i16 (and (trunc (bfe Int32Regs:$a, imm:$oa, 8)), 255)),
// i1 compare -> i32
def : Pat<(i32 (setne i1:$a, i1:$b)),
- (SELP_u32ii -1, 0, (XORb1rr Int1Regs:$a, Int1Regs:$b))>;
+ (SELP_u32ii -1, 0, (XORb1rr $a, $b))>;
def : Pat<(i32 (setne i1:$a, i1:$b)),
- (SELP_u32ii 0, -1, (XORb1rr Int1Regs:$a, Int1Regs:$b))>;
+ (SELP_u32ii 0, -1, (XORb1rr $a, $b))>;
multiclass FSET_FORMAT<PatFrag OpNode, PatLeaf Mode, PatLeaf ModeFTZ> {
// f16 -> pred
def : Pat<(i1 (OpNode f16:$a, f16:$b)),
- (SETP_f16rr Int16Regs:$a, Int16Regs:$b, ModeFTZ)>,
+ (SETP_f16rr $a, $b, ModeFTZ)>,
Requires<[useFP16Math,doF32FTZ]>;
def : Pat<(i1 (OpNode f16:$a, f16:$b)),
- (SETP_f16rr Int16Regs:$a, Int16Regs:$b, Mode)>,
+ (SETP_f16rr $a, $b, Mode)>,
Requires<[useFP16Math]>;
// bf16 -> pred
def : Pat<(i1 (OpNode bf16:$a, bf16:$b)),
- (SETP_bf16rr Int16Regs:$a, Int16Regs:$b, ModeFTZ)>,
+ (SETP_bf16rr $a, $b, ModeFTZ)>,
Requires<[hasBF16Math,doF32FTZ]>;
def : Pat<(i1 (OpNode bf16:$a, bf16:$b)),
- (SETP_bf16rr Int16Regs:$a, Int16Regs:$b, Mode)>,
+ (SETP_bf16rr $a, $b, Mode)>,
Requires<[hasBF16Math]>;
// f32 -> pred
def : Pat<(i1 (OpNode f32:$a, f32:$b)),
- (SETP_f32rr Float32Regs:$a, Float32Regs:$b, ModeFTZ)>,
+ (SETP_f32rr $a, $b, ModeFTZ)>,
Requires<[doF32FTZ]>;
def : Pat<(i1 (OpNode f32:$a, f32:$b)),
- (SETP_f32rr Float32Regs:$a, Float32Regs:$b, Mode)>;
+ (SETP_f32rr $a, $b, Mode)>;
def : Pat<(i1 (OpNode Float32Regs:$a, fpimm:$b)),
- (SETP_f32ri Float32Regs:$a, fpimm:$b, ModeFTZ)>,
+ (SETP_f32ri $a, fpimm:$b, ModeFTZ)>,
Requires<[doF32FTZ]>;
def : Pat<(i1 (OpNode f32:$a, fpimm:$b)),
- (SETP_f32ri Float32Regs:$a, fpimm:$b, Mode)>;
+ (SETP_f32ri $a, fpimm:$b, Mode)>;
def : Pat<(i1 (OpNode fpimm:$a, f32:$b)),
- (SETP_f32ir fpimm:$a, Float32Regs:$b, ModeFTZ)>,
+ (SETP_f32ir fpimm:$a, $b, ModeFTZ)>,
Requires<[doF32FTZ]>;
def : Pat<(i1 (OpNode fpimm:$a, f32:$b)),
- (SETP_f32ir fpimm:$a, Float32Regs:$b, Mode)>;
+ (SETP_f32ir fpimm:$a, $b, Mode)>;
// f64 -> pred
def : Pat<(i1 (OpNode f64:$a, f64:$b)),
- (SETP_f64rr Float64Regs:$a, Float64Regs:$b, Mode)>;
+ (SETP_f64rr $a, $b, Mode)>;
def : Pat<(i1 (OpNode f64:$a, fpimm:$b)),
- (SETP_f64ri Float64Reg...
[truncated]
|
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These types in the output dag of a Pat do not impact the generated matcher code at all. Removing them makes for more concise and readable code.