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[ARM] Record store with pre/post-indexed addressing as mayStore #121565

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Merged
merged 2 commits into from
Jan 7, 2025
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[ARM] Record store with pre/post-indexed addressing as mayStore #121565

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7810e6a
[ARM] Introduce test for PR121565 (NFC)
antoniofrighetto Jan 7, 2025
446a426
[ARM] Record store with pre/post-indexed addressing as `mayStore`
antoniofrighetto Jan 7, 2025
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3 changes: 2 additions & 1 deletion llvm/lib/Target/ARM/ARMInstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -3320,7 +3320,7 @@ def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
}



let mayStore = 1, hasSideEffects = 0 in {
def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
(ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre,
StMiscFrm, IIC_iStore_bh_ru,
Expand Down Expand Up @@ -3352,6 +3352,7 @@ def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
let Inst{3-0} = offset{3-0}; // imm3_0/Rm
let DecoderMethod = "DecodeAddrMode3Instruction";
}
} // mayStore = 1, hasSideEffects = 0

let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in {
def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
Expand Down
41 changes: 41 additions & 0 deletions llvm/test/CodeGen/ARM/sink-store-pre-load-dependency.mir
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@@ -0,0 +1,41 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -o - %s -mtriple=armv7-- -run-pass=machine-sink | FileCheck %s

name: sink-store-load-dep
tracksRegLiveness: true
stack:
- { id: 0, type: default, size: 8, alignment: 8 }
body: |
bb.0:
; CHECK-LABEL: name: sink-store-load-dep
; CHECK: bb.0:
; CHECK: [[LDRi12_:%[0-9]+]]:gpr = LDRi12 %stack.0, 0, 14 /* CC::al */, $noreg :: (load (s32))
; CHECK-NEXT: [[MOVi:%[0-9]+]]:gpr = MOVi 55296, 14 /* CC::al */, $noreg, $noreg
; CHECK-NEXT: [[ADDri1:%[0-9]+]]:gpr = ADDri [[LDRi12_:%[0-9]+]], 0, 14 /* CC::al */, $noreg, $noreg
; CHECK-NEXT: [[LDRH:%[0-9]+]]:gpr = LDRH killed [[ADDri1:%[0-9]+]], $noreg, 0, 14 /* CC::al */, $noreg :: (load (s16))
; CHECK-NEXT: [[MOVi1:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK-NEXT: early-clobber %5:gpr = STRH_PRE [[MOVi:%[0-9]+]], [[LDRi12_:%[0-9]+]], [[MOVi1:%[0-9]+]], 0, 14 /* CC::al */, $noreg
; CHECK-NEXT: [[SUBri:%.*]]:gpr = SUBri killed [[LDRi12_:%[0-9]+]], 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: bb.2:
; CHECK-NEXT: [[MOVi2:%[0-9]+]]:gpr = MOVi [[LDRH:%[0-9]+]], 14 /* CC::al */, $noreg, $noreg
%0:gpr = LDRi12 %stack.0, 0, 14, $noreg :: (load (s32))
%1:gpr = MOVi 55296, 14, $noreg, $noreg
%2:gpr = ADDri %0:gpr, 0, 14, $noreg, $noreg
%3:gpr = LDRH killed %2:gpr, $noreg, 0, 14, $noreg :: (load (s16))
%4:gpr = MOVi 0, 14, $noreg, $noreg
early-clobber %5:gpr = STRH_PRE %1:gpr, %0:gpr, %4:gpr, 0, 14, $noreg
%6:gpr = SUBri killed %0:gpr, 0, 14, $noreg, $noreg
CMPri %6:gpr, 0, 14, $noreg, implicit-def $cpsr
Bcc %bb.2, 3, $cpsr
B %bb.1

bb.1:
%8:gpr = MOVi 0, 14, $noreg, $noreg
$r0 = COPY %8:gpr
BX_RET 14, $noreg, implicit $r0

bb.2:
%9:gpr = MOVi %3:gpr, 14, $noreg, $noreg
$r0 = COPY %9:gpr
BX_RET 14, $noreg, implicit $r0
...
6 changes: 3 additions & 3 deletions llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s
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Expand Up @@ -325,11 +325,11 @@
# CHECK-NEXT: 2 1 1.00 * strd r4, r5, [r12], -r10
# CHECK-NEXT: 1 1 1.00 * strh r3, [r4]
# CHECK-NEXT: 1 1 1.00 * strh r2, [r7, #4]
# CHECK-NEXT: 2 1 1.00 U strh r1, [r8, #64]!
# CHECK-NEXT: 2 1 1.00 * strh r1, [r8, #64]!
# CHECK-NEXT: 2 1 1.00 * strh r12, [sp], #4
# CHECK-NEXT: 1 1 1.00 * strh r6, [r5, r4]
# CHECK-NEXT: 2 1 1.00 U strh r3, [r8, r11]!
# CHECK-NEXT: 2 1 1.00 U strh r1, [r2, -r1]!
# CHECK-NEXT: 2 1 1.00 * strh r3, [r8, r11]!
# CHECK-NEXT: 2 1 1.00 * strh r1, [r2, -r1]!
# CHECK-NEXT: 2 1 1.00 * strh r9, [r7], r2
# CHECK-NEXT: 2 1 1.00 * strh r4, [r3], -r2
# CHECK-NEXT: 2 1 1.00 U strht r2, [r5], #76
Expand Down
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