[InstCombine][NFC] Precommit a test for folding a binary op of reductions. #121568

mgudim · 2025-01-03T13:04:49Z

No description provided.

llvmbot · 2025-01-03T13:05:25Z

@llvm/pr-subscribers-llvm-transforms

Author: Mikhail Gudim (mgudim)

Changes

Full diff: https://github.com/llvm/llvm-project/pull/121568.diff

1 Files Affected:

(added) llvm/test/Transforms/InstCombine/fold-binop-of-reductions.ll (+100)

diff --git a/llvm/test/Transforms/InstCombine/fold-binop-of-reductions.ll b/llvm/test/Transforms/InstCombine/fold-binop-of-reductions.ll
new file mode 100644
index 00000000000000..ad47165d100156
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/fold-binop-of-reductions.ll
@@ -0,0 +1,100 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt < %s -passes=instcombine -S | FileCheck %s
+target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128"
+
+define i32 @add_of_reduce_add(<16 x i32> %v0, <16 x i32> %v1) {
+; CHECK-LABEL: define i32 @add_of_reduce_add(
+; CHECK-SAME: <16 x i32> [[V0:%.*]], <16 x i32> [[V1:%.*]]) {
+; CHECK-NEXT:    [[V0_RED:%.*]] = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[V0]])
+; CHECK-NEXT:    [[V1_RED:%.*]] = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[V1]])
+; CHECK-NEXT:    [[RES:%.*]] = add i32 [[V0_RED]], [[V1_RED]]
+; CHECK-NEXT:    ret i32 [[RES]]
+;
+  %v0_red = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %v0)
+  %v1_red = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %v1)
+  %res = add i32 %v0_red, %v1_red
+  ret i32 %res
+}
+
+define i32 @sub_of_reduce_add(<16 x i32> %v0, <16 x i32> %v1) {
+; CHECK-LABEL: define i32 @sub_of_reduce_add(
+; CHECK-SAME: <16 x i32> [[V0:%.*]], <16 x i32> [[V1:%.*]]) {
+; CHECK-NEXT:    [[TMP1:%.*]] = sub <16 x i32> [[V0]], [[V1]]
+; CHECK-NEXT:    [[RES:%.*]] = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[TMP1]])
+; CHECK-NEXT:    ret i32 [[RES]]
+;
+  %v0_red = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %v0)
+  %v1_red = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %v1)
+  %res = sub i32 %v0_red, %v1_red
+  ret i32 %res
+}
+
+define i32 @mul_of_reduce_mul(<16 x i32> %v0, <16 x i32> %v1) {
+; CHECK-LABEL: define i32 @mul_of_reduce_mul(
+; CHECK-SAME: <16 x i32> [[V0:%.*]], <16 x i32> [[V1:%.*]]) {
+; CHECK-NEXT:    [[V0_RED:%.*]] = tail call i32 @llvm.vector.reduce.mul.v16i32(<16 x i32> [[V0]])
+; CHECK-NEXT:    [[V1_RED:%.*]] = tail call i32 @llvm.vector.reduce.mul.v16i32(<16 x i32> [[V1]])
+; CHECK-NEXT:    [[RES:%.*]] = mul i32 [[V0_RED]], [[V1_RED]]
+; CHECK-NEXT:    ret i32 [[RES]]
+;
+  %v0_red = tail call i32 @llvm.vector.reduce.mul.v16i32(<16 x i32> %v0)
+  %v1_red = tail call i32 @llvm.vector.reduce.mul.v16i32(<16 x i32> %v1)
+  %res = mul i32 %v0_red, %v1_red
+  ret i32 %res
+}
+
+define i32 @and_of_reduce_and(<16 x i32> %v0, <16 x i32> %v1) {
+; CHECK-LABEL: define i32 @and_of_reduce_and(
+; CHECK-SAME: <16 x i32> [[V0:%.*]], <16 x i32> [[V1:%.*]]) {
+; CHECK-NEXT:    [[V0_RED:%.*]] = tail call i32 @llvm.vector.reduce.and.v16i32(<16 x i32> [[V0]])
+; CHECK-NEXT:    [[V1_RED:%.*]] = tail call i32 @llvm.vector.reduce.and.v16i32(<16 x i32> [[V1]])
+; CHECK-NEXT:    [[RES:%.*]] = and i32 [[V0_RED]], [[V1_RED]]
+; CHECK-NEXT:    ret i32 [[RES]]
+;
+  %v0_red = tail call i32 @llvm.vector.reduce.and.v16i32(<16 x i32> %v0)
+  %v1_red = tail call i32 @llvm.vector.reduce.and.v16i32(<16 x i32> %v1)
+  %res = and i32 %v0_red, %v1_red
+  ret i32 %res
+}
+
+define i32 @or_of_reduce_or(<16 x i32> %v0, <16 x i32> %v1) {
+; CHECK-LABEL: define i32 @or_of_reduce_or(
+; CHECK-SAME: <16 x i32> [[V0:%.*]], <16 x i32> [[V1:%.*]]) {
+; CHECK-NEXT:    [[V0_RED:%.*]] = tail call i32 @llvm.vector.reduce.or.v16i32(<16 x i32> [[V0]])
+; CHECK-NEXT:    [[V1_RED:%.*]] = tail call i32 @llvm.vector.reduce.or.v16i32(<16 x i32> [[V1]])
+; CHECK-NEXT:    [[RES:%.*]] = or i32 [[V0_RED]], [[V1_RED]]
+; CHECK-NEXT:    ret i32 [[RES]]
+;
+  %v0_red = tail call i32 @llvm.vector.reduce.or.v16i32(<16 x i32> %v0)
+  %v1_red = tail call i32 @llvm.vector.reduce.or.v16i32(<16 x i32> %v1)
+  %res = or i32 %v0_red, %v1_red
+  ret i32 %res
+}
+
+define i32 @xor_of_reduce_xor(<16 x i32> %v0, <16 x i32> %v1) {
+; CHECK-LABEL: define i32 @xor_of_reduce_xor(
+; CHECK-SAME: <16 x i32> [[V0:%.*]], <16 x i32> [[V1:%.*]]) {
+; CHECK-NEXT:    [[V0_RED:%.*]] = tail call i32 @llvm.vector.reduce.xor.v16i32(<16 x i32> [[V0]])
+; CHECK-NEXT:    [[V1_RED:%.*]] = tail call i32 @llvm.vector.reduce.xor.v16i32(<16 x i32> [[V1]])
+; CHECK-NEXT:    [[RES:%.*]] = xor i32 [[V0_RED]], [[V1_RED]]
+; CHECK-NEXT:    ret i32 [[RES]]
+;
+  %v0_red = tail call i32 @llvm.vector.reduce.xor.v16i32(<16 x i32> %v0)
+  %v1_red = tail call i32 @llvm.vector.reduce.xor.v16i32(<16 x i32> %v1)
+  %res = xor i32 %v0_red, %v1_red
+  ret i32 %res
+}
+
+define i32 @add_of_reduce_mul(<16 x i32> %v0, <16 x i32> %v1) {
+; CHECK-LABEL: define i32 @add_of_reduce_mul(
+; CHECK-SAME: <16 x i32> [[V0:%.*]], <16 x i32> [[V1:%.*]]) {
+; CHECK-NEXT:    [[V0_RED:%.*]] = tail call i32 @llvm.vector.reduce.mul.v16i32(<16 x i32> [[V0]])
+; CHECK-NEXT:    [[V1_RED:%.*]] = tail call i32 @llvm.vector.reduce.mul.v16i32(<16 x i32> [[V1]])
+; CHECK-NEXT:    [[RES:%.*]] = xor i32 [[V0_RED]], [[V1_RED]]
+; CHECK-NEXT:    ret i32 [[RES]]
+;
+  %v0_red = tail call i32 @llvm.vector.reduce.mul.v16i32(<16 x i32> %v0)
+  %v1_red = tail call i32 @llvm.vector.reduce.mul.v16i32(<16 x i32> %v1)
+  %res = xor i32 %v0_red, %v1_red
+  ret i32 %res
+}

dtcxzyw

Can you add a negative test with mismatched vector types?

llvm/test/Transforms/InstCombine/fold-binop-of-reductions.ll

goldsteinn · 2025-01-03T18:15:41Z

Can you add a negative test with mismatched vector types?

Also multi use tests (that should fail).

nikic · 2025-01-08T11:57:57Z

llvm/test/Transforms/InstCombine/fold-binop-of-reductions.ll

Please also add negative tests where intrinsic IDs are not the same or vector types don't match, and add a test that should flags are not preserved.

Please also add negative tests where intrinsic IDs are not the same

I cannot find this test.

reduction_does_not_match_binop

I guess nikic means to add a test like reduce.mul + reduce.add.

right, just realized that and pushed.

mgudim · 2025-01-08T22:30:01Z

Can you add a negative test with mismatched vector types?

done

mgudim · 2025-01-08T22:30:53Z

Can you add a negative test with mismatched vector types?

Also multi use tests (that should fail).

done.

dtcxzyw

LGTM

dtcxzyw · 2025-01-09T08:06:36Z

llvm/test/Transforms/InstCombine/fold-binop-of-reductions.ll

+  ret i32 %res
+}
+
+define i32 @do_not_preserve_overflow_flags(<16 x i32> %v0, <16 x i32> %v1, ptr %p) {


%p is unused.

fixed it, thanks

dtcxzyw · 2025-01-09T08:06:46Z

llvm/test/Transforms/InstCombine/fold-binop-of-reductions.ll

+  ret i32 %res
+}
+
+define i32 @preserve_disjoint_flags(<16 x i32> %v0, <16 x i32> %v1, ptr %p) {


%p is unused.

fixed it, thanks

nikic

LGTM, though adding one test using scalable vectors probably wouldn't hurt.

mgudim · 2025-01-09T13:13:46Z

LGTM, though adding one test using scalable vectors probably wouldn't hurt.

added vscale tests

mgudim requested review from nikic, michaelmaitland and topperc January 3, 2025 13:04

llvmbot added llvm:instcombine Covers the InstCombine, InstSimplify and AggressiveInstCombine passes llvm:transforms labels Jan 3, 2025

mgudim mentioned this pull request Jan 3, 2025

[VectorCombine] Fold binary op of reductions. #121567

Merged

dtcxzyw reviewed Jan 3, 2025

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llvm/test/Transforms/InstCombine/fold-binop-of-reductions.ll Outdated Show resolved Hide resolved

dtcxzyw changed the title ~~[InstCombine] Precommit a test for folding a binary op of reductions.~~ [InstCombine][NFC] Precommit a test for folding a binary op of reductions. Jan 3, 2025

nikic reviewed Jan 8, 2025

View reviewed changes

mgudim force-pushed the test_binop_reduce branch 2 times, most recently from abe25d4 to f161113 Compare January 8, 2025 22:29

mgudim force-pushed the test_binop_reduce branch 2 times, most recently from 48f9a77 to 364f0bb Compare January 9, 2025 08:00

dtcxzyw approved these changes Jan 9, 2025

View reviewed changes

mgudim force-pushed the test_binop_reduce branch from 364f0bb to 2faa49e Compare January 9, 2025 08:13

nikic approved these changes Jan 9, 2025

View reviewed changes

[InstCombine] Precommit a test for folding a binary op of reductions.

a9ee495

mgudim force-pushed the test_binop_reduce branch from 2faa49e to a9ee495 Compare January 9, 2025 13:12

mgudim merged commit c87ef14 into llvm:main Jan 9, 2025
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[InstCombine][NFC] Precommit a test for folding a binary op of reductions. #121568

[InstCombine][NFC] Precommit a test for folding a binary op of reductions. #121568

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