Skip to content

[llvm] Remove br i1 undef from regression tests #121733

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 3 commits into from
Jan 6, 2025
Merged

[llvm] Remove br i1 undef from regression tests #121733

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
d0dc53a
Remove br i1 undef tests in X86/AMX
leewei05 Jan 6, 2025
f350ba2
Remove br i1 undef tests
leewei05 Jan 6, 2025
84a5621
Replace undef with poison
leewei05 Jan 6, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/X86/2011-06-03-x87chain.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -30,9 +30,9 @@ entry:
ret float %conv
}

define void @PR17495() {
define void @PR17495(i1 %arg) {
entry:
br i1 undef, label %while.end, label %while.body
br i1 %arg, label %while.end, label %while.body

while.body: ; preds = %while.body, %entry
%x.1.copyload = load i24, ptr undef, align 1
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/X86/2020_12_02_decrementing_loop.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -165,7 +165,7 @@ failure: ; preds = %backedge
unreachable
}

define void @test_04() {
define void @test_04(i32 %arg) {
; CHECK-LABEL: test_04:
; CHECK: ## %bb.0: ## %bb
; CHECK-NEXT: ud2
Expand All @@ -175,7 +175,7 @@ bb:
bb1: ; preds = %bb10, %bb
%tmp = phi i64 [ 1, %bb ], [ %tmp2, %bb10 ]
%tmp2 = add nuw nsw i64 %tmp, 1
br i1 undef, label %bb21, label %bb7
br i1 poison, label %bb21, label %bb7

bb7: ; preds = %bb1
%tmp8 = add nsw i64 %tmp, -1
Expand All @@ -187,7 +187,7 @@ bb10: ; preds = %bb16
br label %bb1

bb11: ; preds = %bb16, %bb7
switch i32 undef, label %bb19 [
switch i32 %arg, label %bb19 [
i32 0, label %bb17
i32 1, label %bb16
i32 2, label %bb15
Expand All @@ -205,7 +205,7 @@ bb15: ; preds = %bb11
unreachable

bb16: ; preds = %bb11
br i1 undef, label %bb10, label %bb11
br i1 poison, label %bb10, label %bb11

bb17: ; preds = %bb11
unreachable
Expand Down
76 changes: 38 additions & 38 deletions llvm/test/CodeGen/X86/AMX/amx-combine-undef.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -5,13 +5,13 @@ define void @undef_2phi(ptr%buf) {
; CHECK-LABEL: @undef_2phi(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32)
; CHECK-NEXT: br i1 undef, label [[L1:%.*]], label [[L2:%.*]]
; CHECK-NEXT: br i1 poison, label [[L1:%.*]], label [[L2:%.*]]
; CHECK: l1:
; CHECK-NEXT: [[T1:%.*]] = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32)
; CHECK-NEXT: br i1 undef, label [[L2]], label [[L3:%.*]]
; CHECK-NEXT: br i1 poison, label [[L2]], label [[L3:%.*]]
; CHECK: l2:
; CHECK-NEXT: [[TMP1:%.*]] = phi x86_amx [ [[TMP0]], [[ENTRY:%.*]] ], [ [[T1]], [[L1]] ]
; CHECK-NEXT: br i1 undef, label [[L3]], label [[EXIT:%.*]]
; CHECK-NEXT: br i1 poison, label [[L3]], label [[EXIT:%.*]]
; CHECK: l3:
; CHECK-NEXT: [[TMP2:%.*]] = phi x86_amx [ [[TMP1]], [[L2]] ], [ [[T1]], [[L1]] ]
; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 8, i16 32, ptr [[BUF:%.*]], i64 1024, x86_amx [[TMP2]])
Expand All @@ -20,16 +20,16 @@ define void @undef_2phi(ptr%buf) {
; CHECK-NEXT: ret void
;
entry:
br i1 undef, label %l1, label %l2
br i1 poison, label %l1, label %l2

l1:
%t1 = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32)
%t2 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %t1)
br i1 undef, label %l2, label %l3
br i1 poison, label %l2, label %l3

l2:
%t3 = phi <256 x i32> [ undef, %entry ], [ %t2, %l1 ]
br i1 undef, label %l3, label %exit
%t3 = phi <256 x i32> [ poison, %entry ], [ %t2, %l1 ]
br i1 poison, label %l3, label %exit

l3:
%t4 = phi <256 x i32> [ %t3, %l2], [ %t2, %l1 ]
Expand All @@ -45,10 +45,10 @@ define void @foo_undef(ptr%buf) {
; CHECK-LABEL: @foo_undef(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32)
; CHECK-NEXT: br i1 undef, label [[L1:%.*]], label [[L2:%.*]]
; CHECK-NEXT: br i1 poison, label [[L1:%.*]], label [[L2:%.*]]
; CHECK: l1:
; CHECK-NEXT: [[T1:%.*]] = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32)
; CHECK-NEXT: br i1 undef, label [[L2]], label [[EXIT:%.*]]
; CHECK-NEXT: br i1 poison, label [[L2]], label [[EXIT:%.*]]
; CHECK: l2:
; CHECK-NEXT: [[TMP1:%.*]] = phi x86_amx [ [[TMP0]], [[ENTRY:%.*]] ], [ [[T1]], [[L1]] ]
; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 8, i16 32, ptr [[BUF:%.*]], i64 1024, x86_amx [[TMP1]])
Expand All @@ -57,15 +57,15 @@ define void @foo_undef(ptr%buf) {
; CHECK-NEXT: ret void
;
entry:
br i1 undef, label %l1, label %l2
br i1 poison, label %l1, label %l2

l1:
%t1 = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32)
%t2 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %t1)
br i1 undef, label %l2, label %exit
br i1 poison, label %l2, label %exit

l2:
%t3 = phi <256 x i32> [ undef, %entry ], [ %t2, %l1 ]
%t3 = phi <256 x i32> [ poison, %entry ], [ %t2, %l1 ]
%t4 = call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> %t3)
call void @llvm.x86.tilestored64.internal(i16 8, i16 32, ptr %buf, i64 1024, x86_amx %t4)
br label %exit
Expand All @@ -78,10 +78,10 @@ define void @foo_zero(ptr%buf) {
; CHECK-LABEL: @foo_zero(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32)
; CHECK-NEXT: br i1 undef, label [[L1:%.*]], label [[L2:%.*]]
; CHECK-NEXT: br i1 poison, label [[L1:%.*]], label [[L2:%.*]]
; CHECK: l1:
; CHECK-NEXT: [[T1:%.*]] = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32)
; CHECK-NEXT: br i1 undef, label [[L2]], label [[EXIT:%.*]]
; CHECK-NEXT: br i1 poison, label [[L2]], label [[EXIT:%.*]]
; CHECK: l2:
; CHECK-NEXT: [[TMP1:%.*]] = phi x86_amx [ [[TMP0]], [[ENTRY:%.*]] ], [ [[T1]], [[L1]] ]
; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 8, i16 32, ptr [[BUF:%.*]], i64 1024, x86_amx [[TMP1]])
Expand All @@ -90,12 +90,12 @@ define void @foo_zero(ptr%buf) {
; CHECK-NEXT: ret void
;
entry:
br i1 undef, label %l1, label %l2
br i1 poison, label %l1, label %l2

l1:
%t1 = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32)
%t2 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %t1)
br i1 undef, label %l2, label %exit
br i1 poison, label %l2, label %exit

l2:
%t3 = phi <256 x i32> [ zeroinitializer, %entry ], [ %t2, %l1 ]
Expand All @@ -112,14 +112,14 @@ define void @foo_vrow(ptr%buf, i16 %row) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = alloca <256 x i32>, align 64
; CHECK-NEXT: [[TMP1:%.*]] = alloca <256 x i32>, align 64
; CHECK-NEXT: br i1 undef, label [[L1:%.*]], label [[L2:%.*]]
; CHECK-NEXT: br i1 poison, label [[L1:%.*]], label [[L2:%.*]]
; CHECK: l1:
; CHECK-NEXT: [[T1:%.*]] = call x86_amx @llvm.x86.tilezero.internal(i16 [[ROW:%.*]], i16 32)
; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 [[ROW]], i16 32, ptr [[TMP1]], i64 32, x86_amx [[T1]])
; CHECK-NEXT: [[TMP3:%.*]] = load <256 x i32>, ptr [[TMP1]], align 1024
; CHECK-NEXT: br i1 undef, label [[L2]], label [[EXIT:%.*]]
; CHECK-NEXT: br i1 poison, label [[L2]], label [[EXIT:%.*]]
; CHECK: l2:
; CHECK-NEXT: [[T3:%.*]] = phi <256 x i32> [ undef, [[ENTRY:%.*]] ], [ [[TMP3]], [[L1]] ]
; CHECK-NEXT: [[T3:%.*]] = phi <256 x i32> [ poison, [[ENTRY:%.*]] ], [ [[TMP3]], [[L1]] ]
; CHECK-NEXT: store <256 x i32> [[T3]], ptr [[TMP0]], align 1024
; CHECK-NEXT: [[TMP5:%.*]] = call x86_amx @llvm.x86.tileloadd64.internal(i16 [[ROW]], i16 32, ptr [[TMP0]], i64 32)
; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 [[ROW]], i16 32, ptr [[BUF:%.*]], i64 1024, x86_amx [[TMP5]])
Expand All @@ -128,15 +128,15 @@ define void @foo_vrow(ptr%buf, i16 %row) {
; CHECK-NEXT: ret void
;
entry:
br i1 undef, label %l1, label %l2
br i1 poison, label %l1, label %l2

l1:
%t1 = call x86_amx @llvm.x86.tilezero.internal(i16 %row, i16 32)
%t2 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %t1)
br i1 undef, label %l2, label %exit
br i1 poison, label %l2, label %exit

l2:
%t3 = phi <256 x i32> [ undef, %entry ], [ %t2, %l1 ]
%t3 = phi <256 x i32> [ poison, %entry ], [ %t2, %l1 ]
%t4 = call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> %t3)
call void @llvm.x86.tilestored64.internal(i16 %row, i16 32, ptr %buf, i64 1024, x86_amx %t4)
br label %exit
Expand All @@ -150,13 +150,13 @@ define void @foo_vcol(ptr%buf, i16 %col) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = alloca <256 x i32>, align 64
; CHECK-NEXT: [[TMP1:%.*]] = alloca <256 x i32>, align 64
; CHECK-NEXT: br i1 undef, label [[L1:%.*]], label [[L2:%.*]]
; CHECK-NEXT: br i1 poison, label [[L1:%.*]], label [[L2:%.*]]
; CHECK: l1:
; CHECK-NEXT: [[T1:%.*]] = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 [[COL:%.*]])
; CHECK-NEXT: [[TMP3:%.*]] = sext i16 [[COL]] to i64
; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 8, i16 [[COL]], ptr [[TMP1]], i64 [[TMP3]], x86_amx [[T1]])
; CHECK-NEXT: [[TMP4:%.*]] = load <256 x i32>, ptr [[TMP1]], align 1024
; CHECK-NEXT: br i1 undef, label [[L2]], label [[EXIT:%.*]]
; CHECK-NEXT: br i1 poison, label [[L2]], label [[EXIT:%.*]]
; CHECK: l2:
; CHECK-NEXT: [[T3:%.*]] = phi <256 x i32> [ zeroinitializer, [[ENTRY:%.*]] ], [ [[TMP4]], [[L1]] ]
; CHECK-NEXT: store <256 x i32> [[T3]], ptr [[TMP0]], align 1024
Expand All @@ -168,12 +168,12 @@ define void @foo_vcol(ptr%buf, i16 %col) {
; CHECK-NEXT: ret void
;
entry:
br i1 undef, label %l1, label %l2
br i1 poison, label %l1, label %l2

l1:
%t1 = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 %col)
%t2 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %t1)
br i1 undef, label %l2, label %exit
br i1 poison, label %l2, label %exit

l2:
%t3 = phi <256 x i32> [ zeroinitializer, %entry ], [ %t2, %l1 ]
Expand All @@ -189,29 +189,29 @@ define void @noshape(ptr%buf) {
; CHECK-LABEL: @noshape(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = alloca <256 x i32>, align 64
; CHECK-NEXT: br i1 undef, label [[L1:%.*]], label [[L2:%.*]]
; CHECK-NEXT: br i1 poison, label [[L1:%.*]], label [[L2:%.*]]
; CHECK: l1:
; CHECK-NEXT: [[T1:%.*]] = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32)
; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 8, i16 32, ptr [[TMP0]], i64 32, x86_amx [[T1]])
; CHECK-NEXT: [[TMP2:%.*]] = load <256 x i32>, ptr [[TMP0]], align 1024
; CHECK-NEXT: br i1 undef, label [[L2]], label [[EXIT:%.*]]
; CHECK-NEXT: br i1 poison, label [[L2]], label [[EXIT:%.*]]
; CHECK: l2:
; CHECK-NEXT: [[T3:%.*]] = phi <256 x i32> [ undef, [[ENTRY:%.*]] ], [ [[TMP2]], [[L1]] ]
; CHECK-NEXT: [[T3:%.*]] = phi <256 x i32> [ poison, [[ENTRY:%.*]] ], [ [[TMP2]], [[L1]] ]
; CHECK-NEXT: store <256 x i32> [[T3]], ptr [[BUF:%.*]], align 1024
; CHECK-NEXT: br label [[EXIT]]
; CHECK: exit:
; CHECK-NEXT: ret void
;
entry:
br i1 undef, label %l1, label %l2
br i1 poison, label %l1, label %l2

l1:
%t1 = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32)
%t2 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %t1)
br i1 undef, label %l2, label %exit
br i1 poison, label %l2, label %exit

l2:
%t3 = phi <256 x i32> [ undef, %entry ], [ %t2, %l1 ]
%t3 = phi <256 x i32> [ poison, %entry ], [ %t2, %l1 ]
%t4 = call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> %t3)
%t5 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %t4)
store <256 x i32> %t5, ptr %buf
Expand All @@ -225,30 +225,30 @@ define void @noshape2(ptr%buf) {
; CHECK-LABEL: @noshape2(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = alloca <256 x i32>, align 64
; CHECK-NEXT: br i1 undef, label [[L1:%.*]], label [[L2:%.*]]
; CHECK-NEXT: br i1 poison, label [[L1:%.*]], label [[L2:%.*]]
; CHECK: l1:
; CHECK-NEXT: [[T1:%.*]] = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32)
; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 8, i16 32, ptr [[TMP0]], i64 32, x86_amx [[T1]])
; CHECK-NEXT: [[TMP2:%.*]] = load <256 x i32>, ptr [[TMP0]], align 1024
; CHECK-NEXT: br i1 undef, label [[L2]], label [[EXIT:%.*]]
; CHECK-NEXT: br i1 poison, label [[L2]], label [[EXIT:%.*]]
; CHECK: l2:
; CHECK-NEXT: [[T3:%.*]] = phi <256 x i32> [ undef, [[ENTRY:%.*]] ], [ [[TMP2]], [[L1]] ]
; CHECK-NEXT: [[T3:%.*]] = phi <256 x i32> [ poison, [[ENTRY:%.*]] ], [ [[TMP2]], [[L1]] ]
; CHECK-NEXT: [[T6:%.*]] = call <256 x i32> @llvm.abs.v256i32(<256 x i32> [[T3]], i1 true)
; CHECK-NEXT: store <256 x i32> [[T6]], ptr [[BUF:%.*]], align 1024
; CHECK-NEXT: br label [[EXIT]]
; CHECK: exit:
; CHECK-NEXT: ret void
;
entry:
br i1 undef, label %l1, label %l2
br i1 poison, label %l1, label %l2

l1:
%t1 = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32)
%t2 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %t1)
br i1 undef, label %l2, label %exit
br i1 poison, label %l2, label %exit

l2:
%t3 = phi <256 x i32> [ undef, %entry ], [ %t2, %l1 ]
%t3 = phi <256 x i32> [ poison, %entry ], [ %t2, %l1 ]
%t4 = call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> %t3)
%t5 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %t4)
%t6 = call <256 x i32> @llvm.abs.v256i32(<256 x i32> %t5, i1 1)
Expand Down
Loading
Loading