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[LLVM][AArch64] Add new feature +sme-mop4 and +sme-tmop #121935

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Merged
merged 6 commits into from
Jan 14, 2025
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[LLVM][AArch64] Add new feature +sme-mop4 and +sme-tmop #121935

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14cd654
[AArch64] Add new feature +sme-mop4 and +sme-tmop
CarolineConcatto Dec 18, 2024
fc3af4c
Instruction are not available when sme2p2 is enabled
CarolineConcatto Jan 14, 2025
540e2b9
Fix AArch64InstrInfo.td
CarolineConcatto Jan 14, 2025
9cc9808
Run clang format
CarolineConcatto Jan 14, 2025
f0e7480
Add dependency tests for sme-tmop and sme-mop4
CarolineConcatto Jan 14, 2025
1a815f1
Add sme2 test dependency
CarolineConcatto Jan 14, 2025
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10 changes: 8 additions & 2 deletions clang/test/Driver/aarch64-implied-sme-features.c
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Expand Up @@ -53,5 +53,11 @@
// RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+ssve-aes %s -### 2>&1 | FileCheck %s --check-prefix=SVE-AES
// SVE-AES: "-target-feature" "+sme" "-target-feature" "+sme2" "-target-feature" "+ssve-aes" "-target-feature" "+sve-aes"

+// RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+ssve-bitperm %s -### 2>&1 | FileCheck %s --check-prefix=SVE-BITPERM
+// SVE-BITPERM: "-target-feature" "+sme" "-target-feature" "+sme2" "-target-feature" "+ssve-bitperm" "-target-feature" "+sve-bitperm"
// RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+ssve-bitperm %s -### 2>&1 | FileCheck %s --check-prefix=SVE-BITPERM
// SVE-BITPERM: "-target-feature" "+sme" "-target-feature" "+sme2" "-target-feature" "+ssve-bitperm" "-target-feature" "+sve-bitperm"

// RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+sme-tmop %s -### 2>&1 | FileCheck %s --check-prefix=SME-TMOP
// SME-TMOP: "-target-feature" "+sme" "-target-feature" "+sme-tmop" "-target-feature" "+sme2"

// RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+sme-mop4 %s -### 2>&1 | FileCheck %s --check-prefix=SME-MOP4
// SME-MOP4: "-target-feature" "+sme" "-target-feature" "+sme-mop4" "-target-feature" "+sme2"
2 changes: 2 additions & 0 deletions clang/test/Driver/print-supported-extensions-aarch64.c
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Expand Up @@ -71,6 +71,8 @@
// CHECK-NEXT: sme-fa64 FEAT_SME_FA64 Enable the full A64 instruction set in streaming SVE mode
// CHECK-NEXT: sme-i16i64 FEAT_SME_I16I64 Enable Scalable Matrix Extension (SME) I16I64 instructions
// CHECK-NEXT: sme-lutv2 FEAT_SME_LUTv2 Enable Scalable Matrix Extension (SME) LUTv2 instructions
// CHECK-NEXT: sme-mop4 FEAT_SME_MOP4 Enable SME Quarter-tile outer product instructions
// CHECK-NEXT: sme-tmop FEAT_SME_TMOP Enable SME Structured sparsity outer product instructions
// CHECK-NEXT: sme2 FEAT_SME2 Enable Scalable Matrix Extension 2 (SME2) instructions
// CHECK-NEXT: sme2p1 FEAT_SME2p1 Enable Scalable Matrix Extension 2.1 instructions
// CHECK-NEXT: sme2p2 FEAT_SME2p2 Enable Armv9.6-A Scalable Matrix Extension 2.2 instructions
Expand Down
3 changes: 2 additions & 1 deletion llvm/lib/Target/AArch64/AArch64.td
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Expand Up @@ -74,7 +74,8 @@ def SVEUnsupported : AArch64Unsupported {
}

let F = [HasSME2p2, HasSVE2p2orSME2p2, HasNonStreamingSVEorSME2p2,
HasNonStreamingSVE2p2orSME2p2, HasNonStreamingSVE2orSSVE_BitPerm] in
HasNonStreamingSVE2p2orSME2p2, HasNonStreamingSVE2orSSVE_BitPerm,
HasSME_MOP4, HasSME_TMOP] in
def SME2p2Unsupported : AArch64Unsupported;

def SME2p1Unsupported : AArch64Unsupported {
Expand Down
6 changes: 6 additions & 0 deletions llvm/lib/Target/AArch64/AArch64Features.td
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Expand Up @@ -570,6 +570,12 @@ def FeaturePoPS: ExtensionWithMArch<"pops", "PoPS", "FEAT_PoPS",
def FeatureSSVE_BitPerm : ExtensionWithMArch<"ssve-bitperm", "SSVE_BitPerm", "FEAT_SSVE_BitPerm",
"Enable Armv9.6-A SVE BitPerm support in streaming SVE mode", [FeatureSME2, FeatureSVEBitPerm]>;

def FeatureSME_MOP4: ExtensionWithMArch<"sme-mop4", "SME_MOP4", "FEAT_SME_MOP4",
"Enable SME Quarter-tile outer product instructions", [FeatureSME2]>;

def FeatureSME_TMOP: ExtensionWithMArch<"sme-tmop", "SME_TMOP", "FEAT_SME_TMOP",
"Enable SME Structured sparsity outer product instructions.", [FeatureSME2]>;

//===----------------------------------------------------------------------===//
// Other Features
//===----------------------------------------------------------------------===//
Expand Down
6 changes: 5 additions & 1 deletion llvm/lib/Target/AArch64/AArch64InstrInfo.td
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Expand Up @@ -206,12 +206,16 @@ def HasSSVE_FP8DOT4 : Predicate<"Subtarget->hasSSVE_FP8DOT4() || "
"ssve-fp8dot4 or (sve2 and fp8dot4)">;
def HasLUT : Predicate<"Subtarget->hasLUT()">,
AssemblerPredicateWithAll<(all_of FeatureLUT), "lut">;
def HasSME_LUTv2 : Predicate<"Subtarget->isStreaming() && Subtarget->hasSME_LUTv2()">,
def HasSME_LUTv2 : Predicate<"Subtarget->isStreaming() && Subtarget->hasSME_LUTv2()">,
AssemblerPredicateWithAll<(all_of FeatureSME_LUTv2), "sme-lutv2">;
def HasSMEF8F16 : Predicate<"Subtarget->isStreaming() && Subtarget->hasSMEF8F16()">,
AssemblerPredicateWithAll<(all_of FeatureSMEF8F16), "sme-f8f16">;
def HasSMEF8F32 : Predicate<"Subtarget->isStreaming() && Subtarget->hasSMEF8F32()">,
AssemblerPredicateWithAll<(all_of FeatureSMEF8F32), "sme-f8f32">;
def HasSME_MOP4 : Predicate<"(Subtarget->isStreaming() && Subtarget->hasSME_MOP4())">,
AssemblerPredicateWithAll<(all_of FeatureSME_MOP4), "sme-mop4">;
def HasSME_TMOP : Predicate<"(Subtarget->isStreaming() && Subtarget->hasSME_TMOP())">,
AssemblerPredicateWithAll<(all_of FeatureSME_TMOP), "sme-tmop">;

def HasCMPBR : Predicate<"Subtarget->hasCMPBR()">,
AssemblerPredicateWithAll<(all_of FeatureCMPBR), "cmpbr">;
Expand Down
53 changes: 32 additions & 21 deletions llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
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Expand Up @@ -147,7 +147,7 @@ defm USMOPA_MPPZZ_D : sme_int_outer_product_i64<0b100, "usmopa", int_aarch64_sme
defm USMOPS_MPPZZ_D : sme_int_outer_product_i64<0b101, "usmops", int_aarch64_sme_usmops_wide>;
}

let Predicates = [HasSME2p2] in {
let Predicates = [HasSME_MOP4] in {
defm SMOP4A : sme_quarter_outer_product_i8_i32<0b0, 0b0, 0b0, "smop4a">;
defm SMOP4S : sme_quarter_outer_product_i8_i32<0b0, 0b0, 0b1, "smop4s">;
defm SUMOP4A : sme_quarter_outer_product_i8_i32<0b0, 0b1, 0b0, "sumop4a">;
Expand All @@ -163,7 +163,7 @@ let Predicates = [HasSME2p2] in {
defm UMOP4S : sme_quarter_outer_product_i16_i32<0b1, 0b1, "umop4s">;
}

let Predicates = [HasSME2p2, HasSMEI16I64] in {
let Predicates = [HasSME_MOP4, HasSMEI16I64] in {
defm SMOP4A : sme_quarter_outer_product_i64<0b0, 0b0, 0b0, "smop4a">;
defm SMOP4S : sme_quarter_outer_product_i64<0b0, 0b0, 0b1, "smop4s">;
defm SUMOP4A : sme_quarter_outer_product_i64<0b0, 0b1, 0b0, "sumop4a">;
Expand All @@ -174,7 +174,7 @@ let Predicates = [HasSME2p2, HasSMEI16I64] in {
defm USMOP4S : sme_quarter_outer_product_i64<0b1, 0b0, 0b1, "usmop4s">;
}

let Predicates = [HasSME2p2] in {
let Predicates = [HasSME_TMOP] in {
def STMOPA_M2ZZZI_BtoS : sme_int_sparse_outer_product_i32<0b00100, ZZ_b_mul_r, ZPR8, "stmopa">;
def STMOPA_M2ZZZI_HtoS : sme_int_sparse_outer_product_i32<0b00101, ZZ_h_mul_r, ZPR16, "stmopa">;
def UTMOPA_M2ZZZI_BtoS : sme_int_sparse_outer_product_i32<0b11100, ZZ_b_mul_r, ZPR8, "utmopa">;
Expand Down Expand Up @@ -1053,41 +1053,52 @@ let Predicates = [HasSME2, HasSVEBFSCALE] in {
defm BFSCALE : sme2_bfscale_multi<"bfscale">;
}

let Predicates = [HasSME2p2] in {
let Predicates = [HasSME_MOP4] in {
defm BFMOP4A : sme2_bfmop4as_widening<0, "bfmop4a">;
defm BFMOP4S : sme2_bfmop4as_widening<1, "bfmop4s">;

defm FMOP4A : sme2_fmop4as_fp16_fp32_widening<0, "fmop4a">;
defm FMOP4S : sme2_fmop4as_fp16_fp32_widening<1, "fmop4s">;

defm FMOP4A : sme2_fmop4as_fp32_non_widening<0, "fmop4a">;
defm FMOP4S : sme2_fmop4as_fp32_non_widening<1, "fmop4s">;
}

let Predicates = [HasSME_TMOP] in {
def FTMOPA_M2ZZZI_HtoS : sme_tmopa_32b<0b11000, ZZ_h_mul_r, ZPR16, "ftmopa">;
def FTMOPA_M2ZZZI_StoS : sme_tmopa_32b<0b00000, ZZ_s_mul_r, ZPR32, "ftmopa">;
def BFTMOPA_M2ZZZI_HtoS : sme_tmopa_32b<0b10000, ZZ_h_mul_r, ZPR16, "bftmopa">;
}

defm BFMOP4A : sme2_bfmop4as_widening<0, "bfmop4a">;
defm BFMOP4S : sme2_bfmop4as_widening<1, "bfmop4s">;

let Predicates = [HasSME2p2] in {
defm FMUL_2ZZ : sme2_multi2_fmul_sm<"fmul">;
defm FMUL_2Z2Z : sme2_multi2_fmul_mm< "fmul">;
defm FMUL_4ZZ : sme2_multi4_fmul_sm<"fmul">;
defm FMUL_4Z4Z : sme2_multi4_fmul_mm< "fmul">;

defm FMOP4A : sme2_fmop4as_fp32_non_widening<0, "fmop4a">;
defm FMOP4S : sme2_fmop4as_fp32_non_widening<1, "fmop4s">;

defm FMOP4A : sme2_fmop4as_fp16_fp32_widening<0, "fmop4a">;
defm FMOP4S : sme2_fmop4as_fp16_fp32_widening<1, "fmop4s">;
}
} // [HasSME2p2]

let Predicates = [HasSME2p2, HasSMEB16B16] in {
let Predicates = [HasSME_TMOP, HasSMEB16B16] in {
def BFTMOPA_M2ZZZI_HtoH : sme_tmopa_16b<0b11001, ZZ_h_mul_r, ZPR16, "bftmopa">;
}

let Predicates = [HasSME2p2, HasSMEF8F32], Uses = [FPMR, FPCR] in {
let Predicates = [HasSME_TMOP, HasSMEF8F32], Uses = [FPMR, FPCR] in {
def FTMOPA_M2ZZZI_BtoS : sme_tmopa_32b<0b01000, ZZ_b_mul_r, ZPR8, "ftmopa">;
}
}

let Predicates = [HasSME2p2, HasSMEF8F16], Uses = [FPMR, FPCR] in {
let Predicates = [HasSME_TMOP, HasSMEF8F16], Uses = [FPMR, FPCR] in {
def FTMOPA_M2ZZZI_BtoH : sme_tmopa_16b<0b01001, ZZ_b_mul_r, ZPR8, "ftmopa">;
}

let Predicates = [HasSME_MOP4, HasSMEF8F16], Uses = [FPMR, FPCR] in {
defm FMOP4A : sme2_fmop4a_fp8_fp16_2way<"fmop4a">;
}

let Predicates = [HasSME2p2, HasSMEF16F16] in {
let Predicates = [HasSME_TMOP, HasSMEF16F16] in {
def FTMOPA_M2ZZZI_HtoH : sme_tmopa_16b<0b10001, ZZ_h_mul_r, ZPR16, "ftmopa">;
}

let Predicates = [HasSME_MOP4, HasSMEF16F16] in {
defm FMOP4A : sme2_fmop4as_fp16_non_widening<0, "fmop4a">;
defm FMOP4S : sme2_fmop4as_fp16_non_widening<1, "fmop4s">;
}
Expand All @@ -1098,17 +1109,17 @@ let Predicates = [HasSME2, HasSVEBFSCALE] in {
}

let Uses = [FPMR, FPCR] in {
let Predicates = [HasSME2p2, HasSMEF8F32] in {
let Predicates = [HasSME_MOP4, HasSMEF8F32] in {
defm FMOP4A : sme2_fmop4a_fp8_fp32_4way<"fmop4a">;
}
}

let Predicates = [HasSME2p2, HasSMEB16B16] in {
let Predicates = [HasSME_MOP4, HasSMEB16B16] in {
defm BFMOP4A : sme2_bfmop4as_non_widening<0, "bfmop4a">;
defm BFMOP4S : sme2_bfmop4as_non_widening<1, "bfmop4s">;
}

let Predicates = [HasSME2p2, HasSMEF64F64] in {
let Predicates = [HasSME_MOP4, HasSMEF64F64] in {
defm FMOP4A : sme2_fmop4as_fp64_non_widening<0, "fmop4a">;
defm FMOP4S : sme2_fmop4as_fp64_non_widening<1, "fmop4s">;
}
2 changes: 2 additions & 0 deletions llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
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Expand Up @@ -3831,6 +3831,8 @@ static const struct Extension {
{"occmo", {AArch64::FeatureOCCMO}},
{"pcdphint", {AArch64::FeaturePCDPHINT}},
{"ssve-bitperm", {AArch64::FeatureSSVE_BitPerm}},
{"sme-mop4", {AArch64::FeatureSME_MOP4}},
{"sme-tmop", {AArch64::FeatureSME_TMOP}},
};

static void setRequiredFeatureString(FeatureBitset FBS, std::string &Str) {
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/MC/AArch64/SME2p2/bfmop4as-non-widening-diagnostics.s
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@@ -1,4 +1,4 @@
// RUN: not llvm-mc -triple=aarch64 -mattr=+sme2p2,+sme-b16b16 < %s 2>&1 | FileCheck %s
// RUN: not llvm-mc -triple=aarch64 -mattr=+sme-mop4,+sme-b16b16 < %s 2>&1 | FileCheck %s

// BFMOP4A

Expand Down
62 changes: 31 additions & 31 deletions llvm/test/MC/AArch64/SME2p2/bfmop4as-non-widening.s
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@@ -1,15 +1,15 @@
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2,+sme-b16b16 < %s \
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-mop4,+sme-b16b16 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2,+sme-b16b16 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2p2,+sme-b16b16 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2,+sme-b16b16 < %s \
// RUN: | llvm-objdump -d --mattr=-sme2p2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-mop4,+sme-b16b16 < %s \
// RUN: | llvm-objdump -d --mattr=+sme-mop4,+sme-b16b16 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-mop4,+sme-b16b16 < %s \
// RUN: | llvm-objdump -d --mattr=-sme-mop4 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// Disassemble encoding and check the re-encoding (-show-encoding) matches.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2,+sme-b16b16 < %s \
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-mop4,+sme-b16b16 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p2,+sme-b16b16 -disassemble -show-encoding \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme-mop4,+sme-b16b16 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST

// BFMOP4A
Expand All @@ -19,79 +19,79 @@
bfmop4a za0.h, z0.h, z16.h // 10000001-00100000-00000000-00001000
// CHECK-INST: bfmop4a za0.h, z0.h, z16.h
// CHECK-ENCODING: [0x08,0x00,0x20,0x81]
// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16
// CHECK-ERROR: instruction requires: sme-b16b16 sme-mop4
// CHECK-UNKNOWN: 81200008 <unknown>

bfmop4a za1.h, z12.h, z24.h // 10000001-00101000-00000001-10001001
// CHECK-INST: bfmop4a za1.h, z12.h, z24.h
// CHECK-ENCODING: [0x89,0x01,0x28,0x81]
// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16
// CHECK-ERROR: instruction requires: sme-b16b16 sme-mop4
// CHECK-UNKNOWN: 81280189 <unknown>

bfmop4a za1.h, z14.h, z30.h // 10000001-00101110-00000001-11001001
// CHECK-INST: bfmop4a za1.h, z14.h, z30.h
// CHECK-ENCODING: [0xc9,0x01,0x2e,0x81]
// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16
// CHECK-ERROR: instruction requires: sme-b16b16 sme-mop4
// CHECK-UNKNOWN: 812e01c9 <unknown>

// Single and multiple vectors

bfmop4a za0.h, z0.h, {z16.h-z17.h} // 10000001-00110000-00000000-00001000
// CHECK-INST: bfmop4a za0.h, z0.h, { z16.h, z17.h }
// CHECK-ENCODING: [0x08,0x00,0x30,0x81]
// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16
// CHECK-ERROR: instruction requires: sme-b16b16 sme-mop4
// CHECK-UNKNOWN: 81300008 <unknown>

bfmop4a za1.h, z12.h, {z24.h-z25.h} // 10000001-00111000-00000001-10001001
// CHECK-INST: bfmop4a za1.h, z12.h, { z24.h, z25.h }
// CHECK-ENCODING: [0x89,0x01,0x38,0x81]
// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16
// CHECK-ERROR: instruction requires: sme-b16b16 sme-mop4
// CHECK-UNKNOWN: 81380189 <unknown>

bfmop4a za1.h, z14.h, {z30.h-z31.h} // 10000001-00111110-00000001-11001001
// CHECK-INST: bfmop4a za1.h, z14.h, { z30.h, z31.h }
// CHECK-ENCODING: [0xc9,0x01,0x3e,0x81]
// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16
// CHECK-ERROR: instruction requires: sme-b16b16 sme-mop4
// CHECK-UNKNOWN: 813e01c9 <unknown>

// Multiple and single vectors

bfmop4a za0.h, {z0.h-z1.h}, z16.h // 10000001-00100000-00000010-00001000
// CHECK-INST: bfmop4a za0.h, { z0.h, z1.h }, z16.h
// CHECK-ENCODING: [0x08,0x02,0x20,0x81]
// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16
// CHECK-ERROR: instruction requires: sme-b16b16 sme-mop4
// CHECK-UNKNOWN: 81200208 <unknown>

bfmop4a za1.h, {z12.h-z13.h}, z24.h // 10000001-00101000-00000011-10001001
// CHECK-INST: bfmop4a za1.h, { z12.h, z13.h }, z24.h
// CHECK-ENCODING: [0x89,0x03,0x28,0x81]
// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16
// CHECK-ERROR: instruction requires: sme-b16b16 sme-mop4
// CHECK-UNKNOWN: 81280389 <unknown>

bfmop4a za1.h, {z14.h-z15.h}, z30.h // 10000001-00101110-00000011-11001001
// CHECK-INST: bfmop4a za1.h, { z14.h, z15.h }, z30.h
// CHECK-ENCODING: [0xc9,0x03,0x2e,0x81]
// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16
// CHECK-ERROR: instruction requires: sme-b16b16 sme-mop4
// CHECK-UNKNOWN: 812e03c9 <unknown>

// Multiple vectors

bfmop4a za0.h, {z0.h-z1.h}, {z16.h-z17.h} // 10000001-00110000-00000010-00001000
// CHECK-INST: bfmop4a za0.h, { z0.h, z1.h }, { z16.h, z17.h }
// CHECK-ENCODING: [0x08,0x02,0x30,0x81]
// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16
// CHECK-ERROR: instruction requires: sme-b16b16 sme-mop4
// CHECK-UNKNOWN: 81300208 <unknown>

bfmop4a za1.h, {z12.h-z13.h}, {z24.h-z25.h} // 10000001-00111000-00000011-10001001
// CHECK-INST: bfmop4a za1.h, { z12.h, z13.h }, { z24.h, z25.h }
// CHECK-ENCODING: [0x89,0x03,0x38,0x81]
// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16
// CHECK-ERROR: instruction requires: sme-b16b16 sme-mop4
// CHECK-UNKNOWN: 81380389 <unknown>

bfmop4a za1.h, {z14.h-z15.h}, {z30.h-z31.h} // 10000001-00111110-00000011-11001001
// CHECK-INST: bfmop4a za1.h, { z14.h, z15.h }, { z30.h, z31.h }
// CHECK-ENCODING: [0xc9,0x03,0x3e,0x81]
// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16
// CHECK-ERROR: instruction requires: sme-b16b16 sme-mop4
// CHECK-UNKNOWN: 813e03c9 <unknown>


Expand All @@ -102,77 +102,77 @@ bfmop4a za1.h, {z14.h-z15.h}, {z30.h-z31.h} // 10000001-00111110-00000011-11001
bfmop4s za0.h, z0.h, z16.h // 10000001-00100000-00000000-00011000
// CHECK-INST: bfmop4s za0.h, z0.h, z16.h
// CHECK-ENCODING: [0x18,0x00,0x20,0x81]
// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16
// CHECK-ERROR: instruction requires: sme-b16b16 sme-mop4
// CHECK-UNKNOWN: 81200018 <unknown>

bfmop4s za1.h, z12.h, z24.h // 10000001-00101000-00000001-10011001
// CHECK-INST: bfmop4s za1.h, z12.h, z24.h
// CHECK-ENCODING: [0x99,0x01,0x28,0x81]
// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16
// CHECK-ERROR: instruction requires: sme-b16b16 sme-mop4
// CHECK-UNKNOWN: 81280199 <unknown>

bfmop4s za1.h, z14.h, z30.h // 10000001-00101110-00000001-11011001
// CHECK-INST: bfmop4s za1.h, z14.h, z30.h
// CHECK-ENCODING: [0xd9,0x01,0x2e,0x81]
// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16
// CHECK-ERROR: instruction requires: sme-b16b16 sme-mop4
// CHECK-UNKNOWN: 812e01d9 <unknown>

// Single and multiple vectors

bfmop4s za0.h, z0.h, {z16.h-z17.h} // 10000001-00110000-00000000-00011000
// CHECK-INST: bfmop4s za0.h, z0.h, { z16.h, z17.h }
// CHECK-ENCODING: [0x18,0x00,0x30,0x81]
// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16
// CHECK-ERROR: instruction requires: sme-b16b16 sme-mop4
// CHECK-UNKNOWN: 81300018 <unknown>

bfmop4s za1.h, z12.h, {z24.h-z25.h} // 10000001-00111000-00000001-10011001
// CHECK-INST: bfmop4s za1.h, z12.h, { z24.h, z25.h }
// CHECK-ENCODING: [0x99,0x01,0x38,0x81]
// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16
// CHECK-ERROR: instruction requires: sme-b16b16 sme-mop4
// CHECK-UNKNOWN: 81380199 <unknown>

bfmop4s za1.h, z14.h, {z30.h-z31.h} // 10000001-00111110-00000001-11011001
// CHECK-INST: bfmop4s za1.h, z14.h, { z30.h, z31.h }
// CHECK-ENCODING: [0xd9,0x01,0x3e,0x81]
// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16
// CHECK-ERROR: instruction requires: sme-b16b16 sme-mop4
// CHECK-UNKNOWN: 813e01d9 <unknown>

// Multiple and single vectors

bfmop4s za0.h, {z0.h-z1.h}, z16.h // 10000001-00100000-00000010-00011000
// CHECK-INST: bfmop4s za0.h, { z0.h, z1.h }, z16.h
// CHECK-ENCODING: [0x18,0x02,0x20,0x81]
// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16
// CHECK-ERROR: instruction requires: sme-b16b16 sme-mop4
// CHECK-UNKNOWN: 81200218 <unknown>

bfmop4s za1.h, {z12.h-z13.h}, z24.h // 10000001-00101000-00000011-10011001
// CHECK-INST: bfmop4s za1.h, { z12.h, z13.h }, z24.h
// CHECK-ENCODING: [0x99,0x03,0x28,0x81]
// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16
// CHECK-ERROR: instruction requires: sme-b16b16 sme-mop4
// CHECK-UNKNOWN: 81280399 <unknown>

bfmop4s za1.h, {z14.h-z15.h}, z30.h // 10000001-00101110-00000011-11011001
// CHECK-INST: bfmop4s za1.h, { z14.h, z15.h }, z30.h
// CHECK-ENCODING: [0xd9,0x03,0x2e,0x81]
// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16
// CHECK-ERROR: instruction requires: sme-b16b16 sme-mop4
// CHECK-UNKNOWN: 812e03d9 <unknown>

// Multiple vectors

bfmop4s za0.h, {z0.h-z1.h}, {z16.h-z17.h} // 10000001-00110000-00000010-00011000
// CHECK-INST: bfmop4s za0.h, { z0.h, z1.h }, { z16.h, z17.h }
// CHECK-ENCODING: [0x18,0x02,0x30,0x81]
// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16
// CHECK-ERROR: instruction requires: sme-b16b16 sme-mop4
// CHECK-UNKNOWN: 81300218 <unknown>

bfmop4s za1.h, {z12.h-z13.h}, {z24.h-z25.h} // 10000001-00111000-00000011-10011001
// CHECK-INST: bfmop4s za1.h, { z12.h, z13.h }, { z24.h, z25.h }
// CHECK-ENCODING: [0x99,0x03,0x38,0x81]
// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16
// CHECK-ERROR: instruction requires: sme-b16b16 sme-mop4
// CHECK-UNKNOWN: 81380399 <unknown>

bfmop4s za1.h, {z14.h-z15.h}, {z30.h-z31.h} // 10000001-00111110-00000011-11011001
// CHECK-INST: bfmop4s za1.h, { z14.h, z15.h }, { z30.h, z31.h }
// CHECK-ENCODING: [0xd9,0x03,0x3e,0x81]
// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16
// CHECK-ERROR: instruction requires: sme-b16b16 sme-mop4
// CHECK-UNKNOWN: 813e03d9 <unknown>
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