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[RISCV][VLOPT] Add mask load to isSupported and getOperandInfo #122030
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@llvm/pr-subscribers-backend-risc-v Author: Michael Maitland (michaelmaitland) ChangesFull diff: https://github.com/llvm/llvm-project/pull/122030.diff 2 Files Affected:
diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
index d7ac3afe7b76b2..2acdefcc6d505d 100644
--- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
@@ -257,6 +257,9 @@ static OperandInfo getOperandInfo(const MachineOperand &MO,
// Vector Unit-Stride Instructions
// Vector Strided Instructions
/// Dest EEW encoded in the instruction and EMUL=(EEW/SEW)*LMUL
+ case RISCV::VLM_V:
+ case RISCV::VSM_V:
+ return OperandInfo(RISCVVType::getEMULEqualsEEWDivSEWTimesLMUL(0, MI), 0);
case RISCV::VLE8_V:
case RISCV::VSE8_V:
case RISCV::VLSE8_V:
@@ -742,6 +745,7 @@ static bool isSupportedInstr(const MachineInstr &MI) {
switch (RVV->BaseInstr) {
// Vector Unit-Stride Instructions
// Vector Strided Instructions
+ case RISCV::VLM_V:
case RISCV::VLE8_V:
case RISCV::VLSE8_V:
case RISCV::VLE16_V:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir b/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
index a1bbfc8a7d3514..689809f6201054 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
@@ -603,6 +603,36 @@ body: |
%x:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1, 3 /* e8 */, 0
...
---
+name: vlm_v
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: vlm_v
+ ; CHECK: %x:vr = PseudoVLM_V_B8 $noreg, $noreg, 1, 0 /* e8 */, 0 /* tu, mu */
+ ; CHECK-NEXT: %y:vr = PseudoVMAND_MM_B8 $noreg, %x, 1, 0 /* e8 */
+ %x:vr = PseudoVLM_V_B8 $noreg, $noreg, -1, 0, 0
+ %y:vr = PseudoVMAND_MM_B8 $noreg, %x, 1, 0
+...
+---
+name: vlm_v_incompatible_eew
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: vlm_v_incompatible_eew
+ ; CHECK: %x:vr = PseudoVLM_V_B8 $noreg, $noreg, -1, 0 /* e8 */, 0 /* tu, mu */
+ ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, $noreg, %x, 1, 4 /* e16 */, 0 /* tu, mu */
+ %x:vr = PseudoVLM_V_B8 $noreg, $noreg, -1, 0, 0
+ %y:vr = PseudoVADD_VV_M1 $noreg, $noreg, %x, 1, 4 /* e16 */, 0
+...
+---
+name: vlm_v_incompatible_emul
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: vlm_v_incompatible_emul
+ ; CHECK: %x:vr = PseudoVLM_V_B8 $noreg, $noreg, -1, 0 /* e8 */, 0 /* tu, mu */
+ ; CHECK-NEXT: %y:vr = PseudoVMAND_MM_B16 $noreg, %x, 1, 0 /* e8 */
+ %x:vr = PseudoVLM_V_B8 $noreg, $noreg, -1, 0, 0
+ %y:vr = PseudoVMAND_MM_B16 $noreg, %x, 1, 0
+...
+---
name: vsseN_v
body: |
bb.0:
|
masked -> mask. "Masked load" would be load of a vector with some elements skipped by the mask. "Mask load" loads a memory location containing a mask. |
done |
@@ -257,6 +257,9 @@ static OperandInfo getOperandInfo(const MachineOperand &MO, | |||
// Vector Unit-Stride Instructions | |||
// Vector Strided Instructions | |||
/// Dest EEW encoded in the instruction and EMUL=(EEW/SEW)*LMUL | |||
case RISCV::VLM_V: | |||
case RISCV::VSM_V: |
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No tests for VSM?
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Added, although I'm not sure that it makes sense to have an incompatible_eew test does it?
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LGTM
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/73/builds/11336 Here is the relevant piece of the build log for the reference
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Add mask store to getOperandInfo since it has the same behavior.