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[SPIRV] Return success when selecting reads and writes. #122162

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Merged
merged 2 commits into from
Jan 13, 2025
Merged

[SPIRV] Return success when selecting reads and writes. #122162

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7c84a9a
[SPIRV] Return success when selecting reads and writes.
s-perron Dec 3, 2024
7565734
Merge branch 'main' into buffer_refactor
s-perron Jan 13, 2025
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72 changes: 41 additions & 31 deletions llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -274,10 +274,10 @@ class SPIRVInstructionSelector : public InstructionSelector {
bool selectHandleFromBinding(Register &ResVReg, const SPIRVType *ResType,
MachineInstr &I) const;

void selectReadImageIntrinsic(Register &ResVReg, const SPIRVType *ResType,
bool selectReadImageIntrinsic(Register &ResVReg, const SPIRVType *ResType,
MachineInstr &I) const;

void selectImageWriteIntrinsic(MachineInstr &I) const;
bool selectImageWriteIntrinsic(MachineInstr &I) const;

// Utilities
std::pair<Register, bool>
Expand Down Expand Up @@ -305,7 +305,7 @@ class SPIRVInstructionSelector : public InstructionSelector {
Register IndexReg, bool IsNonUniform,
MachineIRBuilder MIRBuilder) const;
SPIRVType *widenTypeToVec4(const SPIRVType *Type, MachineInstr &I) const;
void extractSubvector(Register &ResVReg, const SPIRVType *ResType,
bool extractSubvector(Register &ResVReg, const SPIRVType *ResType,
Register &ReadReg, MachineInstr &InsertionPoint) const;
bool BuildCOPY(Register DestReg, Register SrcReg, MachineInstr &I) const;
bool loadVec3BuiltinInputID(SPIRV::BuiltIn::BuiltIn BuiltInValue,
Expand Down Expand Up @@ -3002,12 +3002,10 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
return selectHandleFromBinding(ResVReg, ResType, I);
}
case Intrinsic::spv_resource_store_typedbuffer: {
selectImageWriteIntrinsic(I);
return true;
return selectImageWriteIntrinsic(I);
}
case Intrinsic::spv_resource_load_typedbuffer: {
selectReadImageIntrinsic(ResVReg, ResType, I);
return true;
return selectReadImageIntrinsic(ResVReg, ResType, I);
}
case Intrinsic::spv_discard: {
return selectDiscard(ResVReg, ResType, I);
Expand Down Expand Up @@ -3049,7 +3047,7 @@ bool SPIRVInstructionSelector::selectHandleFromBinding(Register &ResVReg,
.constrainAllUses(TII, TRI, RBI);
}

void SPIRVInstructionSelector::selectReadImageIntrinsic(
bool SPIRVInstructionSelector::selectReadImageIntrinsic(
Register &ResVReg, const SPIRVType *ResType, MachineInstr &I) const {

// If the load of the image is in a different basic block, then
Expand All @@ -3064,35 +3062,40 @@ void SPIRVInstructionSelector::selectReadImageIntrinsic(

uint64_t ResultSize = GR.getScalarOrVectorComponentCount(ResType);
if (ResultSize == 4) {
BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpImageRead))
return BuildMI(*I.getParent(), I, I.getDebugLoc(),
TII.get(SPIRV::OpImageRead))
.addDef(ResVReg)
.addUse(GR.getSPIRVTypeID(ResType))
.addUse(ImageReg)
.addUse(I.getOperand(3).getReg());
return;
.addUse(I.getOperand(3).getReg())
.constrainAllUses(TII, TRI, RBI);
}

SPIRVType *ReadType = widenTypeToVec4(ResType, I);
Register ReadReg = MRI->createVirtualRegister(GR.getRegClass(ReadType));
BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpImageRead))
.addDef(ReadReg)
.addUse(GR.getSPIRVTypeID(ReadType))
.addUse(ImageReg)
.addUse(I.getOperand(3).getReg());
bool Succeed =
BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpImageRead))
.addDef(ReadReg)
.addUse(GR.getSPIRVTypeID(ReadType))
.addUse(ImageReg)
.addUse(I.getOperand(3).getReg())
.constrainAllUses(TII, TRI, RBI);
if (!Succeed)
return false;

if (ResultSize == 1) {
BuildMI(*I.getParent(), I, I.getDebugLoc(),
TII.get(SPIRV::OpCompositeExtract))
return BuildMI(*I.getParent(), I, I.getDebugLoc(),
TII.get(SPIRV::OpCompositeExtract))
.addDef(ResVReg)
.addUse(GR.getSPIRVTypeID(ResType))
.addUse(ReadReg)
.addImm(0);
return;
.addImm(0)
.constrainAllUses(TII, TRI, RBI);
}
extractSubvector(ResVReg, ResType, ReadReg, I);
return extractSubvector(ResVReg, ResType, ReadReg, I);
}

void SPIRVInstructionSelector::extractSubvector(
bool SPIRVInstructionSelector::extractSubvector(
Register &ResVReg, const SPIRVType *ResType, Register &ReadReg,
MachineInstr &InsertionPoint) const {
SPIRVType *InputType = GR.getResultType(ReadReg);
Expand All @@ -3108,12 +3111,16 @@ void SPIRVInstructionSelector::extractSubvector(
const TargetRegisterClass *ScalarRegClass = GR.getRegClass(ScalarType);
for (uint64_t I = 0; I < ResultSize; I++) {
Register ComponentReg = MRI->createVirtualRegister(ScalarRegClass);
BuildMI(*InsertionPoint.getParent(), InsertionPoint,
InsertionPoint.getDebugLoc(), TII.get(SPIRV::OpCompositeExtract))
.addDef(ComponentReg)
.addUse(ScalarType->getOperand(0).getReg())
.addUse(ReadReg)
.addImm(I);
bool Succeed = BuildMI(*InsertionPoint.getParent(), InsertionPoint,
InsertionPoint.getDebugLoc(),
TII.get(SPIRV::OpCompositeExtract))
.addDef(ComponentReg)
.addUse(ScalarType->getOperand(0).getReg())
.addUse(ReadReg)
.addImm(I)
.constrainAllUses(TII, TRI, RBI);
if (!Succeed)
return false;
ComponentRegisters.emplace_back(ComponentReg);
}

Expand All @@ -3125,9 +3132,10 @@ void SPIRVInstructionSelector::extractSubvector(

for (Register ComponentReg : ComponentRegisters)
MIB.addUse(ComponentReg);
return MIB.constrainAllUses(TII, TRI, RBI);
}

void SPIRVInstructionSelector::selectImageWriteIntrinsic(
bool SPIRVInstructionSelector::selectImageWriteIntrinsic(
MachineInstr &I) const {
// If the load of the image is in a different basic block, then
// this will generate invalid code. A proper solution is to move
Expand All @@ -3142,10 +3150,12 @@ void SPIRVInstructionSelector::selectImageWriteIntrinsic(
Register DataReg = I.getOperand(3).getReg();
assert(GR.getResultType(DataReg)->getOpcode() == SPIRV::OpTypeVector);
assert(GR.getScalarOrVectorComponentCount(GR.getResultType(DataReg)) == 4);
BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpImageWrite))
return BuildMI(*I.getParent(), I, I.getDebugLoc(),
TII.get(SPIRV::OpImageWrite))
.addUse(ImageReg)
.addUse(CoordinateReg)
.addUse(DataReg);
.addUse(DataReg)
.constrainAllUses(TII, TRI, RBI);
}

Register SPIRVInstructionSelector::buildPointerToResource(
Expand Down
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