[SelectionDAG][AMDGPU] Negative offset when selecting scratch sv offsets #122251
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
|
@llvm/pr-subscribers-backend-amdgpu Author: None (jofrn) ChangesAPInt will fail when given a negative offset. SelectScratchSVAddr utilizes this function and can be given a negative offset as well, so this change modifies it to use APSInt instead. Full diff: https://github.com/llvm/llvm-project/pull/122251.diff 2 Files Affected:
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index 27e9018d68a03e..44624a2e54f296 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -1926,7 +1926,7 @@ bool AMDGPUDAGToDAGISel::checkFlatScratchSVSSwizzleBug(
KnownBits VKnown = CurDAG->computeKnownBits(VAddr);
KnownBits SKnown =
KnownBits::add(CurDAG->computeKnownBits(SAddr),
- KnownBits::makeConstant(APInt(32, ImmOffset)));
+ KnownBits::makeConstant(APSInt(32, ImmOffset)));
uint64_t VMax = VKnown.getMaxValue().getZExtValue();
uint64_t SMax = SKnown.getMaxValue().getZExtValue();
return (VMax & 3) + (SMax & 3) >= 4;
diff --git a/llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll b/llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
index 066c04b1af088d..77ae03f0d3c324 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
@@ -1243,3 +1243,83 @@ bb:
store volatile i8 4, ptr addrspace(5) %p4
ret void
}
+
+define amdgpu_kernel void @soff1_voff1_negative(i32 %soff) {
+; GFX940-SDAG-LABEL: soff1_voff1_negative:
+; GFX940-SDAG: ; %bb.0: ; %bb
+; GFX940-SDAG-NEXT: s_load_dword s0, s[4:5], 0x24
+; GFX940-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 1
+; GFX940-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX940-SDAG-NEXT: v_add_u32_e32 v0, s0, v0
+; GFX940-SDAG-NEXT: v_add_u32_e32 v0, -1, v0
+; GFX940-SDAG-NEXT: scratch_store_byte v0, v1, off sc0 sc1
+; GFX940-SDAG-NEXT: s_waitcnt vmcnt(0)
+; GFX940-SDAG-NEXT: s_endpgm
+;
+; GFX940-GISEL-LABEL: soff1_voff1_negative:
+; GFX940-GISEL: ; %bb.0: ; %bb
+; GFX940-GISEL-NEXT: s_load_dword s0, s[4:5], 0x24
+; GFX940-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX940-GISEL-NEXT: v_mov_b32_e32 v1, 1
+; GFX940-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX940-GISEL-NEXT: s_add_u32 s0, 0, s0
+; GFX940-GISEL-NEXT: v_add3_u32 v0, s0, v0, -1
+; GFX940-GISEL-NEXT: scratch_store_byte v0, v1, off sc0 sc1
+; GFX940-GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX940-GISEL-NEXT: s_endpgm
+;
+; GFX11-SDAG-LABEL: soff1_voff1_negative:
+; GFX11-SDAG: ; %bb.0: ; %bb
+; GFX11-SDAG-NEXT: s_load_b32 s0, s[4:5], 0x24
+; GFX11-SDAG-NEXT: v_dual_mov_b32 v1, 1 :: v_dual_and_b32 v0, 0x3ff, v0
+; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_add3_u32 v0, 0, s0, v0
+; GFX11-SDAG-NEXT: scratch_store_b8 v0, v1, off offset:-1 dlc
+; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-SDAG-NEXT: s_endpgm
+;
+; GFX11-GISEL-LABEL: soff1_voff1_negative:
+; GFX11-GISEL: ; %bb.0: ; %bb
+; GFX11-GISEL-NEXT: s_load_b32 s0, s[4:5], 0x24
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v1, 1 :: v_dual_and_b32 v0, 0x3ff, v0
+; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-GISEL-NEXT: s_add_u32 s0, 0, s0
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v0, s0, v0
+; GFX11-GISEL-NEXT: scratch_store_b8 v0, v1, off offset:-1 dlc
+; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-GISEL-NEXT: s_endpgm
+;
+; GFX12-SDAG-LABEL: soff1_voff1_negative:
+; GFX12-SDAG: ; %bb.0: ; %bb
+; GFX12-SDAG-NEXT: s_load_b32 s0, s[4:5], 0x24
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v1, 1 :: v_dual_and_b32 v0, 0x3ff, v0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: scratch_store_b8 v0, v1, s0 offset:-1 scope:SCOPE_SYS
+; GFX12-SDAG-NEXT: s_wait_storecnt 0x0
+; GFX12-SDAG-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: soff1_voff1_negative:
+; GFX12-GISEL: ; %bb.0: ; %bb
+; GFX12-GISEL-NEXT: s_load_b32 s0, s[4:5], 0x24
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v1, 1 :: v_dual_and_b32 v0, 0x3ff, v0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: s_add_co_u32 s0, 0, s0
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX12-GISEL-NEXT: v_add_nc_u32_e32 v0, s0, v0
+; GFX12-GISEL-NEXT: scratch_store_b8 v0, v1, off offset:-1 scope:SCOPE_SYS
+; GFX12-GISEL-NEXT: s_wait_storecnt 0x0
+; GFX12-GISEL-NEXT: s_endpgm
+bb:
+ %soff1 = mul i32 %soff, 1
+ %a = alloca i8, i32 64, align 4, addrspace(5)
+ %as = getelementptr i8, ptr addrspace(5) %a, i32 %soff1
+ %voff = call i32 @llvm.amdgcn.workitem.id.x()
+ %voff1 = mul i32 %voff, 1
+ %asv = getelementptr i8, ptr addrspace(5) %as, i32 %voff1
+ %p1 = getelementptr i8, ptr addrspace(5) %asv, i32 -1
+ store volatile i8 1, ptr addrspace(5) %p1
+ ret void
+}
|
jayfoad
reviewed
Jan 9, 2025
| @@ -1926,7 +1926,7 @@ bool AMDGPUDAGToDAGISel::checkFlatScratchSVSSwizzleBug( | |||
| KnownBits VKnown = CurDAG->computeKnownBits(VAddr); | |||
| KnownBits SKnown = | |||
| KnownBits::add(CurDAG->computeKnownBits(SAddr), | |||
| KnownBits::makeConstant(APInt(32, ImmOffset))); | |||
| KnownBits::makeConstant(APSInt(32, ImmOffset))); | |||
There was a problem hiding this comment.
I'd suggest leaving it as APInt but passing /*isSigned=*/ true as the third argument.
jofrn
force-pushed
the
selectsvs-negativeoffset
branch
2 times, most recently
from
4272fae to
8683ff0
Compare
|
✅ With the latest revision this PR passed the C/C++ code formatter. |
jofrn
force-pushed
the
selectsvs-negativeoffset
branch
from
8683ff0 to
39d4fee
Compare
jayfoad
approved these changes
Jan 9, 2025
arsenm
reviewed
Jan 9, 2025
| ; GFX12-GISEL-NEXT: s_wait_storecnt 0x0 | ||
| ; GFX12-GISEL-NEXT: s_endpgm | ||
| bb: | ||
| %soff1 = mul i32 %soff, 1 |
There was a problem hiding this comment.
Is this mum by 1 really doing anything?
| ; GFX12-GISEL-NEXT: s_endpgm | ||
| bb: | ||
| %soff1 = mul i32 %soff, 1 | ||
| %a = alloca i8, i32 64, align 4, addrspace(5) |
There was a problem hiding this comment.
Noncanonical alloca, [64 x i8]
| %a = alloca i8, i32 64, align 4, addrspace(5) | ||
| %as = getelementptr i8, ptr addrspace(5) %a, i32 %soff1 | ||
| %voff = call i32 @llvm.amdgcn.workitem.id.x() | ||
| %voff1 = mul i32 %voff, 1 |
A negative offset will trigger an assertion in checkFlatScratchSVSSwizzleBug. This change modifies it to use isSigned parameter of APInt.
jofrn
force-pushed
the
selectsvs-negativeoffset
branch
from
39d4fee to
1492406
Compare
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/134/builds/11762 Here is the relevant piece of the build log for the reference |
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/73/builds/11749 Here is the relevant piece of the build log for the reference |
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/3/builds/10340 Here is the relevant piece of the build log for the reference |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
APInt will fail when given a negative offset. SelectScratchSVAddr utilizes this function and can be given a negative offset as well, so this change modifies it to use APSInt instead.