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[llvm] Mark scavenging spill-slots as *spilled* stack objects. #122673

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Jan 14, 2025
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[llvm] Mark scavenging spill-slots as *spilled* stack objects. #122673

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2 changes: 1 addition & 1 deletion llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
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Expand Up @@ -3902,7 +3902,7 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
const TargetRegisterClass &RC = AArch64::GPR64RegClass;
unsigned Size = TRI->getSpillSize(RC);
Align Alignment = TRI->getSpillAlign(RC);
int FI = MFI.CreateStackObject(Size, Alignment, false);
int FI = MFI.CreateSpillStackObject(Size, Alignment);
RS->addScavengingFrameIndex(FI);
LLVM_DEBUG(dbgs() << "No available CS registers, allocated fi#" << FI
<< " as the emergency spill slot.\n");
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2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
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Expand Up @@ -1438,7 +1438,7 @@ void SIFrameLowering::processFunctionBeforeFrameFinalized(
// second VGPR emergency frame index.
if (HaveSGPRToVMemSpill &&
allocateScavengingFrameIndexesNearIncomingSP(MF)) {
RS->addScavengingFrameIndex(MFI.CreateStackObject(4, Align(4), false));
RS->addScavengingFrameIndex(MFI.CreateSpillStackObject(4, Align(4)));
}
}
}
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4 changes: 2 additions & 2 deletions llvm/lib/Target/ARC/ARCFrameLowering.cpp
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Expand Up @@ -438,8 +438,8 @@ void ARCFrameLowering::processFunctionBeforeFrameFinalized(
LLVM_DEBUG(dbgs() << "Current stack size: " << MFI.getStackSize() << "\n");
const TargetRegisterClass *RC = &ARC::GPR32RegClass;
if (MFI.hasStackObjects()) {
int RegScavFI = MFI.CreateStackObject(RegInfo->getSpillSize(*RC),
RegInfo->getSpillAlign(*RC), false);
int RegScavFI = MFI.CreateSpillStackObject(RegInfo->getSpillSize(*RC),
RegInfo->getSpillAlign(*RC));
RS->addScavengingFrameIndex(RegScavFI);
LLVM_DEBUG(dbgs() << "Created scavenging index RegScavFI=" << RegScavFI
<< "\n");
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2 changes: 1 addition & 1 deletion llvm/lib/Target/ARM/ARMFrameLowering.cpp
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Expand Up @@ -2925,7 +2925,7 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF,
unsigned Size = TRI->getSpillSize(RC);
Align Alignment = TRI->getSpillAlign(RC);
RS->addScavengingFrameIndex(
MFI.CreateStackObject(Size, Alignment, false));
MFI.CreateSpillStackObject(Size, Alignment));
--RegsNeeded;
}
}
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2 changes: 1 addition & 1 deletion llvm/lib/Target/CSKY/CSKYFrameLowering.cpp
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Expand Up @@ -441,7 +441,7 @@ void CSKYFrameLowering::determineCalleeSaves(MachineFunction &MF,
unsigned size = TRI->getSpillSize(*RC);
Align align = TRI->getSpillAlign(*RC);

RS->addScavengingFrameIndex(MFI.CreateStackObject(size, align, false));
RS->addScavengingFrameIndex(MFI.CreateSpillStackObject(size, align));
}

unsigned FnSize = EstimateFunctionSizeInBytes(MF, *TII);
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4 changes: 2 additions & 2 deletions llvm/lib/Target/LoongArch/LoongArchFrameLowering.cpp
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Expand Up @@ -167,8 +167,8 @@ void LoongArchFrameLowering::processFunctionBeforeFrameFinalized(

// Create emergency spill slots.
for (unsigned i = 0; i < ScavSlotsNum; ++i) {
int FI = MFI.CreateStackObject(RI->getSpillSize(RC), RI->getSpillAlign(RC),
false);
int FI =
MFI.CreateSpillStackObject(RI->getSpillSize(RC), RI->getSpillAlign(RC));
RS->addScavengingFrameIndex(FI);
if (IsLargeFunction && LAFI->getBranchRelaxationSpillFrameIndex() == -1)
LAFI->setBranchRelaxationSpillFrameIndex(FI);
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8 changes: 4 additions & 4 deletions llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
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Expand Up @@ -892,8 +892,8 @@ void MipsSEFrameLowering::determineCalleeSaves(MachineFunction &MF,
// it should be 32-bit.
const TargetRegisterClass &RC = STI.isGP64bit() ?
Mips::GPR64RegClass : Mips::GPR32RegClass;
int FI = MF.getFrameInfo().CreateStackObject(TRI->getSpillSize(RC),
TRI->getSpillAlign(RC), false);
int FI = MF.getFrameInfo().CreateSpillStackObject(TRI->getSpillSize(RC),
TRI->getSpillAlign(RC));
RS->addScavengingFrameIndex(FI);
}

Expand All @@ -908,8 +908,8 @@ void MipsSEFrameLowering::determineCalleeSaves(MachineFunction &MF,

const TargetRegisterClass &RC =
ABI.ArePtrs64bit() ? Mips::GPR64RegClass : Mips::GPR32RegClass;
int FI = MF.getFrameInfo().CreateStackObject(TRI->getSpillSize(RC),
TRI->getSpillAlign(RC), false);
int FI = MF.getFrameInfo().CreateSpillStackObject(TRI->getSpillSize(RC),
TRI->getSpillAlign(RC));
RS->addScavengingFrameIndex(FI);
}

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5 changes: 2 additions & 3 deletions llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
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Expand Up @@ -2307,16 +2307,15 @@ PPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF,
const TargetRegisterInfo &TRI = *Subtarget.getRegisterInfo();
unsigned Size = TRI.getSpillSize(RC);
Align Alignment = TRI.getSpillAlign(RC);
RS->addScavengingFrameIndex(MFI.CreateStackObject(Size, Alignment, false));
RS->addScavengingFrameIndex(MFI.CreateSpillStackObject(Size, Alignment));

// Might we have over-aligned allocas?
bool HasAlVars =
MFI.hasVarSizedObjects() && MFI.getMaxAlign() > getStackAlign();

// These kinds of spills might need two registers.
if (spillsCR(MF) || HasAlVars)
RS->addScavengingFrameIndex(
MFI.CreateStackObject(Size, Alignment, false));
RS->addScavengingFrameIndex(MFI.CreateSpillStackObject(Size, Alignment));
}
}

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4 changes: 2 additions & 2 deletions llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
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Expand Up @@ -1595,8 +1595,8 @@ void RISCVFrameLowering::processFunctionBeforeFrameFinalized(
ScavSlotsNum = std::max(ScavSlotsNum, getScavSlotsNumForRVV(MF));

for (unsigned I = 0; I < ScavSlotsNum; I++) {
int FI = MFI.CreateStackObject(RegInfo->getSpillSize(*RC),
RegInfo->getSpillAlign(*RC), false);
int FI = MFI.CreateSpillStackObject(RegInfo->getSpillSize(*RC),
RegInfo->getSpillAlign(*RC));
RS->addScavengingFrameIndex(FI);

if (IsLargeFunction && RVFI->getBranchRelaxationScratchFrameIndex() == -1)
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8 changes: 4 additions & 4 deletions llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
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Expand Up @@ -457,9 +457,9 @@ void SystemZELFFrameLowering::processFunctionBeforeFrameFinalized(
// Create 2 for the case where both addresses in an MVC are
// out of range.
RS->addScavengingFrameIndex(
MFFrame.CreateStackObject(getPointerSize(), Align(8), false));
MFFrame.CreateSpillStackObject(getPointerSize(), Align(8)));
RS->addScavengingFrameIndex(
MFFrame.CreateStackObject(getPointerSize(), Align(8), false));
MFFrame.CreateSpillStackObject(getPointerSize(), Align(8)));
}

// If R6 is used as an argument register it is still callee saved. If it in
Expand Down Expand Up @@ -1491,8 +1491,8 @@ void SystemZXPLINKFrameLowering::processFunctionBeforeFrameFinalized(
if (!isUInt<12>(MaxReach)) {
// We may need register scavenging slots if some parts of the frame
// are outside the reach of an unsigned 12-bit displacement.
RS->addScavengingFrameIndex(MFFrame.CreateStackObject(8, Align(8), false));
RS->addScavengingFrameIndex(MFFrame.CreateStackObject(8, Align(8), false));
RS->addScavengingFrameIndex(MFFrame.CreateSpillStackObject(8, Align(8)));
RS->addScavengingFrameIndex(MFFrame.CreateSpillStackObject(8, Align(8)));
}
}

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4 changes: 2 additions & 2 deletions llvm/lib/Target/XCore/XCoreFrameLowering.cpp
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Expand Up @@ -576,7 +576,7 @@ processFunctionBeforeFrameFinalized(MachineFunction &MF,
unsigned Size = TRI.getSpillSize(RC);
Align Alignment = TRI.getSpillAlign(RC);
if (XFI->isLargeFrame(MF) || hasFP(MF))
RS->addScavengingFrameIndex(MFI.CreateStackObject(Size, Alignment, false));
RS->addScavengingFrameIndex(MFI.CreateSpillStackObject(Size, Alignment));
if (XFI->isLargeFrame(MF) && !hasFP(MF))
RS->addScavengingFrameIndex(MFI.CreateStackObject(Size, Alignment, false));
RS->addScavengingFrameIndex(MFI.CreateSpillStackObject(Size, Alignment));
}
2 changes: 1 addition & 1 deletion llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp
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Expand Up @@ -276,7 +276,7 @@ void XtensaFrameLowering::processFunctionBeforeFrameFinalized(
unsigned Size = TRI->getSpillSize(RC);
Align Alignment = TRI->getSpillAlign(RC);
for (unsigned I = 0; I < ScavSlotsNum; I++) {
int FI = MFI.CreateStackObject(Size, Alignment, false);
int FI = MFI.CreateSpillStackObject(Size, Alignment);
RS->addScavengingFrameIndex(FI);

if (IsLargeFunction &&
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/PowerPC/alloca-crspill.ll
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Expand Up @@ -53,7 +53,7 @@ declare signext i32 @do_something(ptr)
; CHECK64-NEXT: stack-id: default, callee-saved-register: '', callee-saved-restored: true,
; CHECK64-NEXT: local-offset: 0, debug-info-variable: '', debug-info-expression: '',
; CHECK64-NEXT: debug-info-location: '' }
; CHECK64-NEXT: - { id: 1, name: '', type: default, offset: -16, size: 8, alignment: 8,
; CHECK64-NEXT: - { id: 1, name: '', type: spill-slot, offset: -16, size: 8, alignment: 8,
; CHECK64-NEXT: stack-id: default, callee-saved-register: '', callee-saved-restored: true,
; CHECK64-NEXT: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }

Expand All @@ -72,7 +72,7 @@ declare signext i32 @do_something(ptr)
; CHECK32-NEXT: stack-id: default, callee-saved-register: '', callee-saved-restored: true,
; CHECK32-NEXT: local-offset: 0, debug-info-variable: '', debug-info-expression: '',
; CHECK32-NEXT: debug-info-location: '' }
; CHECK32-NEXT: - { id: 1, name: '', type: default, offset: -8, size: 4, alignment: 4,
; CHECK32-NEXT: - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
; CHECK32-NEXT: stack-id: default, callee-saved-register: '', callee-saved-restored: true,
; CHECK32-NEXT: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }

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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/rvv/addi-rvv-stack-object.mir
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Expand Up @@ -40,7 +40,7 @@ stack:
- { id: 0, name: local0, type: default, offset: 0, size: 16, alignment: 16,
stack-id: scalable-vector, callee-saved-register: '', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
# CHECK: - { id: 2, name: '', type: default, offset: -16, size: 8, alignment: 8,
# CHECK: - { id: 2, name: '', type: spill-slot, offset: -16, size: 8, alignment: 8,
# CHECK: stack-id: default, callee-saved-register: '', callee-saved-restored: true,
# CHECK: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
callSites: []
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