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[RISCV] Don't convert virtual register Register to MCRegister in isCompressibleInst. #122843

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Merged
merged 3 commits into from
Jan 14, 2025
Merged

[RISCV] Don't convert virtual register Register to MCRegister in isCompressibleInst. #122843

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511d0c1
[RISCV] Don't convert virtual register Register to MCRegister in isCo…
topperc Jan 14, 2025
0bbdfa9
fixup! clang-format
topperc Jan 14, 2025
6565272
fixup! check the isCompressibleInst lines in AsmPredicateCombiningRIS…
topperc Jan 14, 2025
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51 changes: 41 additions & 10 deletions llvm/test/TableGen/AsmPredicateCombiningRISCV.td
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Original file line number Diff line number Diff line change
Expand Up @@ -60,40 +60,71 @@ def BigInst : RVInst<1, [AsmPred1]>;
def SmallInst1 : RVInst16<1, []>;
def : CompressPat<(BigInst Regs:$r), (SmallInst1 Regs:$r), [AsmPred1]>;
// COMPRESS: if (STI.getFeatureBits()[arch::AsmCond1] &&
// COMPRESS-NEXT: (MI.getOperand(0).isReg()) &&
// COMPRESS-NEXT: (archMCRegisterClasses[arch::RegsRegClassID].contains(MI.getOperand(0).getReg()))) {
// COMPRESS-NEXT: MI.getOperand(0).isReg() &&
// COMPRESS-NEXT: archMCRegisterClasses[arch::RegsRegClassID].contains(MI.getOperand(0).getReg())) {
// COMPRESS-NEXT: // SmallInst1 $r

def SmallInst2 : RVInst16<2, []>;
def : CompressPat<(BigInst Regs:$r), (SmallInst2 Regs:$r), [AsmPred2]>;
// COMPRESS: if (STI.getFeatureBits()[arch::AsmCond2a] &&
// COMPRESS-NEXT: STI.getFeatureBits()[arch::AsmCond2b] &&
// COMPRESS-NEXT: (MI.getOperand(0).isReg()) &&
// COMPRESS-NEXT: (archMCRegisterClasses[arch::RegsRegClassID].contains(MI.getOperand(0).getReg()))) {
// COMPRESS-NEXT: MI.getOperand(0).isReg() &&
// COMPRESS-NEXT: archMCRegisterClasses[arch::RegsRegClassID].contains(MI.getOperand(0).getReg())) {
// COMPRESS-NEXT: // SmallInst2 $r

def SmallInst3 : RVInst16<2, []>;
def : CompressPat<(BigInst Regs:$r), (SmallInst3 Regs:$r), [AsmPred3]>;
// COMPRESS: if ((STI.getFeatureBits()[arch::AsmCond3a] || STI.getFeatureBits()[arch::AsmCond3b]) &&
// COMPRESS-NEXT: (MI.getOperand(0).isReg()) &&
// COMPRESS-NEXT: (archMCRegisterClasses[arch::RegsRegClassID].contains(MI.getOperand(0).getReg()))) {
// COMPRESS-NEXT: MI.getOperand(0).isReg() &&
// COMPRESS-NEXT: archMCRegisterClasses[arch::RegsRegClassID].contains(MI.getOperand(0).getReg())) {
// COMPRESS-NEXT: // SmallInst3 $r

def SmallInst4 : RVInst16<2, []>;
def : CompressPat<(BigInst Regs:$r), (SmallInst4 Regs:$r), [AsmPred1, AsmPred2]>;
// COMPRESS: if (STI.getFeatureBits()[arch::AsmCond1] &&
// COMPRESS-NEXT: STI.getFeatureBits()[arch::AsmCond2a] &&
// COMPRESS-NEXT: STI.getFeatureBits()[arch::AsmCond2b] &&
// COMPRESS-NEXT: (MI.getOperand(0).isReg()) &&
// COMPRESS-NEXT: (archMCRegisterClasses[arch::RegsRegClassID].contains(MI.getOperand(0).getReg()))) {
// COMPRESS-NEXT: MI.getOperand(0).isReg() &&
// COMPRESS-NEXT: archMCRegisterClasses[arch::RegsRegClassID].contains(MI.getOperand(0).getReg())) {
// COMPRESS-NEXT: // SmallInst4 $r

def SmallInst5 : RVInst16<2, []>;
def : CompressPat<(BigInst Regs:$r), (SmallInst5 Regs:$r), [AsmPred1, AsmPred3]>;
// COMPRESS: if (STI.getFeatureBits()[arch::AsmCond1] &&
// COMPRESS-NEXT: (STI.getFeatureBits()[arch::AsmCond3a] || STI.getFeatureBits()[arch::AsmCond3b]) &&
// COMPRESS-NEXT: (MI.getOperand(0).isReg()) &&
// COMPRESS-NEXT: (archMCRegisterClasses[arch::RegsRegClassID].contains(MI.getOperand(0).getReg()))) {
// COMPRESS-NEXT: MI.getOperand(0).isReg() &&
// COMPRESS-NEXT: archMCRegisterClasses[arch::RegsRegClassID].contains(MI.getOperand(0).getReg())) {
// COMPRESS-NEXT: // SmallInst5 $r

// COMPRESS-LABEL: static bool uncompressInst

// COMPRESS-LABEL: static bool isCompressibleInst

// COMPRESS: if (STI.getFeatureBits()[arch::AsmCond1] &&
// COMPRESS-NEXT: MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() &&
// COMPRESS-NEXT: archMCRegisterClasses[arch::RegsRegClassID].contains(MI.getOperand(0).getReg())) {
// COMPRESS-NEXT: // SmallInst1 $r

// COMPRESS: if (STI.getFeatureBits()[arch::AsmCond2a] &&
// COMPRESS-NEXT: STI.getFeatureBits()[arch::AsmCond2b] &&
// COMPRESS-NEXT: MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() &&
// COMPRESS-NEXT: archMCRegisterClasses[arch::RegsRegClassID].contains(MI.getOperand(0).getReg())) {
// COMPRESS-NEXT: // SmallInst2 $r

// COMPRESS: if ((STI.getFeatureBits()[arch::AsmCond3a] || STI.getFeatureBits()[arch::AsmCond3b]) &&
// COMPRESS-NEXT: MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() &&
// COMPRESS-NEXT: archMCRegisterClasses[arch::RegsRegClassID].contains(MI.getOperand(0).getReg())) {
// COMPRESS-NEXT: // SmallInst3 $r

// COMPRESS: if (STI.getFeatureBits()[arch::AsmCond1] &&
// COMPRESS-NEXT: STI.getFeatureBits()[arch::AsmCond2a] &&
// COMPRESS-NEXT: STI.getFeatureBits()[arch::AsmCond2b] &&
// COMPRESS-NEXT: MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() &&
// COMPRESS-NEXT: archMCRegisterClasses[arch::RegsRegClassID].contains(MI.getOperand(0).getReg())) {
// COMPRESS-NEXT: // SmallInst4 $r

// COMPRESS: if (STI.getFeatureBits()[arch::AsmCond1] &&
// COMPRESS-NEXT: (STI.getFeatureBits()[arch::AsmCond3a] || STI.getFeatureBits()[arch::AsmCond3b]) &&
// COMPRESS-NEXT: MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() &&
// COMPRESS-NEXT: archMCRegisterClasses[arch::RegsRegClassID].contains(MI.getOperand(0).getReg())) {
// COMPRESS-NEXT: // SmallInst5 $r
18 changes: 11 additions & 7 deletions llvm/utils/TableGen/CompressInstEmitter.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -773,13 +773,17 @@ void CompressInstEmitter::emitCompressInstEmitter(raw_ostream &OS,
// This is a register operand. Check the register class.
// Don't check register class if this is a tied operand, it was done
// for the operand its tied to.
if (DestOperand.getTiedRegister() == -1)
CondStream.indent(6)
<< "(MI.getOperand(" << OpIdx << ").isReg()) &&\n"
<< " (" << TargetName << "MCRegisterClasses[" << TargetName
<< "::" << ClassRec->getName()
<< "RegClassID].contains(MI.getOperand(" << OpIdx
<< ").getReg())) &&\n";
if (DestOperand.getTiedRegister() == -1) {
CondStream.indent(6) << "MI.getOperand(" << OpIdx << ").isReg()";
if (EType == EmitterType::CheckCompress)
CondStream << " && MI.getOperand(" << OpIdx
<< ").getReg().isPhysical()";
CondStream << " &&\n"
<< indent(6) << TargetName << "MCRegisterClasses["
<< TargetName << "::" << ClassRec->getName()
<< "RegClassID].contains(MI.getOperand(" << OpIdx
<< ").getReg()) &&\n";
}

if (CompressOrUncompress)
CodeStream.indent(6)
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