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[TableGen] Avoid repeated hash lookups (NFC) #123161
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[TableGen] Avoid repeated hash lookups (NFC) #123161
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@llvm/pr-subscribers-tablegen @llvm/pr-subscribers-llvm-globalisel Author: Kazu Hirata (kazutakahirata) ChangesFull diff: https://github.com/llvm/llvm-project/pull/123161.diff 1 Files Affected:
diff --git a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
index a81f2b53f2846e..d56623ed60b36d 100644
--- a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
+++ b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
@@ -875,10 +875,8 @@ unsigned RuleMatcher::getInsnVarID(InstructionMatcher &InsnMatcher) const {
}
void RuleMatcher::defineOperand(StringRef SymbolicName, OperandMatcher &OM) {
- if (!DefinedOperands.contains(SymbolicName)) {
- DefinedOperands[SymbolicName] = &OM;
+ if (DefinedOperands.try_emplace(SymbolicName, &OM).second)
return;
- }
// If the operand is already defined, then we must ensure both references in
// the matcher have the exact same node.
@@ -889,8 +887,7 @@ void RuleMatcher::defineOperand(StringRef SymbolicName, OperandMatcher &OM) {
}
void RuleMatcher::definePhysRegOperand(const Record *Reg, OperandMatcher &OM) {
- if (!PhysRegOperands.contains(Reg))
- PhysRegOperands[Reg] = &OM;
+ PhysRegOperands.try_emplace(Reg, &OM);
}
InstructionMatcher &
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/197/builds/723 Here is the relevant piece of the build log for the reference
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