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merged 2 commits into from
Jan 17, 2025
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[X86][APX] Support APX + MOVRS #123264

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b3149e3
[X86][APX] Support APX + MOVRS
phoebewang Jan 17, 2025
23d4f1d
Change APXF to EGPR
phoebewang Jan 17, 2025
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4 changes: 2 additions & 2 deletions llvm/lib/Target/X86/X86InstrAVX10.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1767,9 +1767,9 @@ multiclass vmovrs_p<bits<8> opc, string OpStr, X86VectorVTInfo _> {
}

multiclass vmovrs_p_vl<bits<8> opc, string OpStr, AVX512VLVectorVTInfo _Vec> {
let Predicates = [HasMOVRS, HasAVX10_2_512] in
let Predicates = [HasMOVRS, HasAVX10_2_512, In64BitMode] in
defm Z : vmovrs_p<opc, OpStr, _Vec.info512>, EVEX_V512;
let Predicates = [HasMOVRS, HasAVX10_2] in {
let Predicates = [HasMOVRS, HasAVX10_2, In64BitMode] in {
defm Z128 : vmovrs_p<opc, OpStr, _Vec.info128>, EVEX_V128;
defm Z256 : vmovrs_p<opc, OpStr, _Vec.info256>, EVEX_V256;
}
Expand Down
21 changes: 19 additions & 2 deletions llvm/lib/Target/X86/X86InstrMisc.td
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Expand Up @@ -1733,7 +1733,7 @@ def CLDEMOTE : I<0x1C, MRM0m, (outs), (ins i8mem:$src), "cldemote\t$src",
//

let SchedRW = [WriteLoad] in {
let Predicates = [HasMOVRS, NoEGPR] in {
let Predicates = [HasMOVRS, NoEGPR, In64BitMode] in {
def MOVRS8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
"movrs{b}\t{$src, $dst|$dst, $src}",
[(set GR8:$dst, (int_x86_movrsqi addr:$src))]>, T8;
Expand All @@ -1746,8 +1746,25 @@ def MOVRS32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
def MOVRS64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
"movrs{q}\t{$src, $dst|$dst, $src}",
[(set GR64:$dst, (int_x86_movrsdi addr:$src))]>, T8;
}

let Predicates = [HasMOVRS] in
def PREFETCHRST2 : I<0x18, MRM4m, (outs), (ins i8mem:$src),
"prefetchrst2\t$src",
[(int_x86_prefetchrs addr:$src)]>, TB;

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Should we share the code with non-EVEX variant?

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Do you have any idea how to handle the difference between OpSize16/OpSize32 and PD?

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@KanRobert KanRobert Jan 17, 2025 •
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Just extract the common part into a class and add OpSize16/32 or PD separately like what we did in X86InstrArithmetic.td ?

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The way in X86InstrArithmetic.td just makes it shared within the same legacy or EVEX definition. It cannot share code between legacy and EVEX.

let Predicates = [HasMOVRS, HasEGPR, In64BitMode] in {
def MOVRS8rm_EVEX : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
"movrs{b}\t{$src, $dst|$dst, $src}",
[(set GR8:$dst, (int_x86_movrsqi addr:$src))]>, EVEX, NoCD8, T_MAP4;
def MOVRS16rm_EVEX : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
"movrs{w}\t{$src, $dst|$dst, $src}",
[(set GR16:$dst, (int_x86_movrshi addr:$src))]>, EVEX, NoCD8, PD, T_MAP4;
def MOVRS32rm_EVEX : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
"movrs{l}\t{$src, $dst|$dst, $src}",
[(set GR32:$dst, (int_x86_movrssi addr:$src))]>, EVEX, NoCD8, T_MAP4;
def MOVRS64rm_EVEX : I<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
"movrs{q}\t{$src, $dst|$dst, $src}",
[(set GR64:$dst, (int_x86_movrsdi addr:$src))]>, EVEX, NoCD8, T_MAP4, REX_W;
}
}
}
21 changes: 21 additions & 0 deletions llvm/test/CodeGen/X86/movrs-builtins.ll
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Original file line number Diff line number Diff line change
@@ -1,11 +1,17 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+movrs | FileCheck %s
; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+movrs,+egpr | FileCheck %s --check-prefix=EGPR

define i8 @test_movrs_si8(ptr %__A) {
; CHECK-LABEL: test_movrs_si8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movrsb (%rdi), %al # encoding: [0x0f,0x38,0x8a,0x07]
; CHECK-NEXT: retq # encoding: [0xc3]
;
; EGPR-LABEL: test_movrs_si8:
; EGPR: # %bb.0: # %entry
; EGPR-NEXT: movrsb (%rdi), %al # EVEX TO LEGACY Compression encoding: [0x0f,0x38,0x8a,0x07]
; EGPR-NEXT: retq # encoding: [0xc3]
entry:
%0 = call i8 @llvm.x86.movrsqi(ptr %__A)
ret i8 %0
Expand All @@ -17,6 +23,11 @@ define i16 @test_movrs_si16(ptr %__A) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movrsw (%rdi), %ax # encoding: [0x66,0x0f,0x38,0x8b,0x07]
; CHECK-NEXT: retq # encoding: [0xc3]
;
; EGPR-LABEL: test_movrs_si16:
; EGPR: # %bb.0: # %entry
; EGPR-NEXT: movrsw (%rdi), %ax # EVEX TO LEGACY Compression encoding: [0x66,0x0f,0x38,0x8b,0x07]
; EGPR-NEXT: retq # encoding: [0xc3]
entry:
%0 = call i16 @llvm.x86.movrshi(ptr %__A)
ret i16 %0
Expand All @@ -28,6 +39,11 @@ define i32 @test_movrs_si32(ptr %__A) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movrsl (%rdi), %eax # encoding: [0x0f,0x38,0x8b,0x07]
; CHECK-NEXT: retq # encoding: [0xc3]
;
; EGPR-LABEL: test_movrs_si32:
; EGPR: # %bb.0: # %entry
; EGPR-NEXT: movrsl (%rdi), %eax # EVEX TO LEGACY Compression encoding: [0x0f,0x38,0x8b,0x07]
; EGPR-NEXT: retq # encoding: [0xc3]
entry:
%0 = call i32 @llvm.x86.movrssi(ptr %__A)
ret i32 %0
Expand All @@ -39,6 +55,11 @@ define i64 @test_movrs_si64(ptr %__A) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movrsq (%rdi), %rax # encoding: [0x48,0x0f,0x38,0x8b,0x07]
; CHECK-NEXT: retq # encoding: [0xc3]
;
; EGPR-LABEL: test_movrs_si64:
; EGPR: # %bb.0: # %entry
; EGPR-NEXT: movrsq (%rdi), %rax # EVEX TO LEGACY Compression encoding: [0x48,0x0f,0x38,0x8b,0x07]
; EGPR-NEXT: retq # encoding: [0xc3]
entry:
%0 = call i64 @llvm.x86.movrsdi(ptr %__A)
ret i64 %0
Expand Down
98 changes: 97 additions & 1 deletion llvm/test/MC/Disassembler/X86/movrs.txt
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Expand Up @@ -95,4 +95,100 @@

# ATT: movrsq -128(%rdx), %rbx
# INTEL: movrs rbx, qword ptr [rdx - 128]
0x48,0x0f,0x38,0x8b,0x5a,0x80
0x48,0x0f,0x38,0x8b,0x5a,0x80

# ATT: movrsb 268435456(%rbp,%r14,8), %r16b
# INTEL: movrs r16b, byte ptr [rbp + 8*r14 + 268435456]
0x62,0xa4,0x7c,0x08,0x8a,0x84,0xf5,0x00,0x00,0x00,0x10

# ATT: movrsb 291(%r17,%rax,4), %bl
# INTEL: movrs bl, byte ptr [r17 + 4*rax + 291]
0x62,0xfc,0x7c,0x08,0x8a,0x9c,0x81,0x23,0x01,0x00,0x00

# ATT: movrsb (%rip), %bl
# INTEL: movrs bl, byte ptr [rip]
0x62,0xf4,0x7c,0x08,0x8a,0x1d,0x00,0x00,0x00,0x00

# ATT: movrsb -32(,%rbp,2), %r18b
# INTEL: movrs r18b, byte ptr [2*rbp - 32]
0x62,0xe4,0x7c,0x08,0x8a,0x14,0x6d,0xe0,0xff,0xff,0xff

# ATT: movrsb 127(%r19), %bl
# INTEL: movrs bl, byte ptr [r19 + 127]
0x62,0xfc,0x7c,0x08,0x8a,0x5b,0x7f

# ATT: movrsb -128(%r20,%riz), %bl
# INTEL: movrs bl, byte ptr [r20 + riz - 128]
0x62,0xfc,0x7c,0x08,0x8a,0x5c,0x24,0x80

# ATT: movrsw 268435456(%rbp,%r14,8), %r16w
# INTEL: movrs r16w, word ptr [rbp + 8*r14 + 268435456]
0x62,0xa4,0x7d,0x08,0x8b,0x84,0xf5,0x00,0x00,0x00,0x10

# ATT: movrsw 291(%r17,%rax,4), %bx
# INTEL: movrs bx, word ptr [r17 + 4*rax + 291]
0x62,0xfc,0x7d,0x08,0x8b,0x9c,0x81,0x23,0x01,0x00,0x00

# ATT: movrsw (%rip), %bx
# INTEL: movrs bx, word ptr [rip]
0x62,0xf4,0x7d,0x08,0x8b,0x1d,0x00,0x00,0x00,0x00

# ATT: movrsw -32(,%rbp,2), %r18w
# INTEL: movrs r18w, word ptr [2*rbp - 32]
0x62,0xe4,0x7d,0x08,0x8b,0x14,0x6d,0xe0,0xff,0xff,0xff

# ATT: movrsw 127(%r19), %bx
# INTEL: movrs bx, word ptr [r19 + 127]
0x62,0xfc,0x7d,0x08,0x8b,0x5b,0x7f

# ATT: movrsw -128(%r20,%riz), %bx
# INTEL: movrs bx, word ptr [r20 + riz - 128]
0x62,0xfc,0x7d,0x08,0x8b,0x5c,0x24,0x80

# ATT: movrsl 268435456(%rbp,%r14,8), %r16d
# INTEL: movrs r16d, dword ptr [rbp + 8*r14 + 268435456]
0x62,0xa4,0x7c,0x08,0x8b,0x84,0xf5,0x00,0x00,0x00,0x10

# ATT: movrsl 291(%r17,%rax,4), %ebx
# INTEL: movrs ebx, dword ptr [r17 + 4*rax + 291]
0x62,0xfc,0x7c,0x08,0x8b,0x9c,0x81,0x23,0x01,0x00,0x00

# ATT: movrsl (%rip), %ebx
# INTEL: movrs ebx, dword ptr [rip]
0x62,0xf4,0x7c,0x08,0x8b,0x1d,0x00,0x00,0x00,0x00

# ATT: movrsl -32(,%rbp,2), %r18d
# INTEL: movrs r18d, dword ptr [2*rbp - 32]
0x62,0xe4,0x7c,0x08,0x8b,0x14,0x6d,0xe0,0xff,0xff,0xff

# ATT: movrsl 127(%r19), %ebx
# INTEL: movrs ebx, dword ptr [r19 + 127]
0x62,0xfc,0x7c,0x08,0x8b,0x5b,0x7f

# ATT: movrsl -128(%r20,%riz), %ebx
# INTEL: movrs ebx, dword ptr [r20 + riz - 128]
0x62,0xfc,0x7c,0x08,0x8b,0x5c,0x24,0x80

# ATT: movrsq 268435456(%rbp,%r14,8), %r16
# INTEL: movrs r16, qword ptr [rbp + 8*r14 + 268435456]
0x62,0xa4,0xfc,0x08,0x8b,0x84,0xf5,0x00,0x00,0x00,0x10

# ATT: movrsq 291(%r17,%rax,4), %rbx
# INTEL: movrs rbx, qword ptr [r17 + 4*rax + 291]
0x62,0xfc,0xfc,0x08,0x8b,0x9c,0x81,0x23,0x01,0x00,0x00

# ATT: movrsq (%rip), %rbx
# INTEL: movrs rbx, qword ptr [rip]
0x62,0xf4,0xfc,0x08,0x8b,0x1d,0x00,0x00,0x00,0x00

# ATT: movrsq -32(,%rbp,2), %r18
# INTEL: movrs r18, qword ptr [2*rbp - 32]
0x62,0xe4,0xfc,0x08,0x8b,0x14,0x6d,0xe0,0xff,0xff,0xff

# ATT: movrsq 127(%r19), %rbx
# INTEL: movrs rbx, qword ptr [r19 + 127]
0x62,0xfc,0xfc,0x08,0x8b,0x5b,0x7f

# ATT: movrsq -128(%r20,%riz), %rbx
# INTEL: movrs rbx, qword ptr [r20 + riz - 128]
0x62,0xfc,0xfc,0x08,0x8b,0x5c,0x24,0x80
98 changes: 97 additions & 1 deletion llvm/test/MC/X86/movrs-att-64.s
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Expand Up @@ -94,4 +94,100 @@

// CHECK: movrsq -128(%rdx), %rbx
// CHECK: encoding: [0x48,0x0f,0x38,0x8b,0x5a,0x80]
movrs -128(%rdx), %rbx
movrs -128(%rdx), %rbx

// CHECK: movrsb 268435456(%rbp,%r14,8), %r16b
// CHECK: encoding: [0x62,0xa4,0x7c,0x08,0x8a,0x84,0xf5,0x00,0x00,0x00,0x10]
movrs 268435456(%rbp,%r14,8), %r16b

// CHECK: movrsb 291(%r17,%rax,4), %bl
// CHECK: encoding: [0x62,0xfc,0x7c,0x08,0x8a,0x9c,0x81,0x23,0x01,0x00,0x00]
movrs 291(%r17,%rax,4), %bl

// CHECK: {evex} movrsb (%rip), %bl
// CHECK: encoding: [0x62,0xf4,0x7c,0x08,0x8a,0x1d,0x00,0x00,0x00,0x00]
{evex} movrs (%rip), %bl

// CHECK: movrsb -32(,%rbp,2), %r18b
// CHECK: encoding: [0x62,0xe4,0x7c,0x08,0x8a,0x14,0x6d,0xe0,0xff,0xff,0xff]
movrs -32(,%rbp,2), %r18b

// CHECK: movrsb 127(%r19), %bl
// CHECK: encoding: [0x62,0xfc,0x7c,0x08,0x8a,0x5b,0x7f]
movrs 127(%r19), %bl

// CHECK: movrsb -128(%r20), %bl
// CHECK: encoding: [0x62,0xfc,0x7c,0x08,0x8a,0x5c,0x24,0x80]
movrs -128(%r20), %bl

// CHECK: movrsw 268435456(%rbp,%r14,8), %r16w
// CHECK: encoding: [0x62,0xa4,0x7d,0x08,0x8b,0x84,0xf5,0x00,0x00,0x00,0x10]
movrs 268435456(%rbp,%r14,8), %r16w

// CHECK: movrsw 291(%r17,%rax,4), %bx
// CHECK: encoding: [0x62,0xfc,0x7d,0x08,0x8b,0x9c,0x81,0x23,0x01,0x00,0x00]
movrs 291(%r17,%rax,4), %bx

// CHECK: {evex} movrsw (%rip), %bx
// CHECK: encoding: [0x62,0xf4,0x7d,0x08,0x8b,0x1d,0x00,0x00,0x00,0x00]
{evex} movrs (%rip), %bx

// CHECK: movrsw -32(,%rbp,2), %r18w
// CHECK: encoding: [0x62,0xe4,0x7d,0x08,0x8b,0x14,0x6d,0xe0,0xff,0xff,0xff]
movrs -32(,%rbp,2), %r18w

// CHECK: movrsw 127(%r19), %bx
// CHECK: encoding: [0x62,0xfc,0x7d,0x08,0x8b,0x5b,0x7f]
movrs 127(%r19), %bx

// CHECK: movrsw -128(%r20), %bx
// CHECK: encoding: [0x62,0xfc,0x7d,0x08,0x8b,0x5c,0x24,0x80]
movrs -128(%r20), %bx

// CHECK: movrsl 268435456(%rbp,%r14,8), %r16d
// CHECK: encoding: [0x62,0xa4,0x7c,0x08,0x8b,0x84,0xf5,0x00,0x00,0x00,0x10]
movrs 268435456(%rbp,%r14,8), %r16d

// CHECK: movrsl 291(%r17,%rax,4), %ebx
// CHECK: encoding: [0x62,0xfc,0x7c,0x08,0x8b,0x9c,0x81,0x23,0x01,0x00,0x00]
movrs 291(%r17,%rax,4), %ebx

// CHECK: {evex} movrsl (%rip), %ebx
// CHECK: encoding: [0x62,0xf4,0x7c,0x08,0x8b,0x1d,0x00,0x00,0x00,0x00]
{evex} movrs (%rip), %ebx

// CHECK: movrsl -32(,%rbp,2), %r18d
// CHECK: encoding: [0x62,0xe4,0x7c,0x08,0x8b,0x14,0x6d,0xe0,0xff,0xff,0xff]
movrs -32(,%rbp,2), %r18d

// CHECK: movrsl 127(%r19), %ebx
// CHECK: encoding: [0x62,0xfc,0x7c,0x08,0x8b,0x5b,0x7f]
movrs 127(%r19), %ebx

// CHECK: movrsl -128(%r20), %ebx
// CHECK: encoding: [0x62,0xfc,0x7c,0x08,0x8b,0x5c,0x24,0x80]
movrs -128(%r20), %ebx

// CHECK: movrsq 268435456(%rbp,%r14,8), %r16
// CHECK: encoding: [0x62,0xa4,0xfc,0x08,0x8b,0x84,0xf5,0x00,0x00,0x00,0x10]
movrs 268435456(%rbp,%r14,8), %r16

// CHECK: movrsq 291(%r17,%rax,4), %rbx
// CHECK: encoding: [0x62,0xfc,0xfc,0x08,0x8b,0x9c,0x81,0x23,0x01,0x00,0x00]
movrs 291(%r17,%rax,4), %rbx

// CHECK: {evex} movrsq (%rip), %rbx
// CHECK: encoding: [0x62,0xf4,0xfc,0x08,0x8b,0x1d,0x00,0x00,0x00,0x00]
{evex} movrs (%rip), %rbx

// CHECK: movrsq -32(,%rbp,2), %r18
// CHECK: encoding: [0x62,0xe4,0xfc,0x08,0x8b,0x14,0x6d,0xe0,0xff,0xff,0xff]
movrs -32(,%rbp,2), %r18

// CHECK: movrsq 127(%r19), %rbx
// CHECK: encoding: [0x62,0xfc,0xfc,0x08,0x8b,0x5b,0x7f]
movrs 127(%r19), %rbx

// CHECK: movrsq -128(%r20), %rbx
// CHECK: encoding: [0x62,0xfc,0xfc,0x08,0x8b,0x5c,0x24,0x80]
movrs -128(%r20), %rbx
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