[X86][AMX-AVX512][NFC] Remove P from intrinsic and instruction name #123270
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@llvm/pr-subscribers-mc @llvm/pr-subscribers-clang Author: Phoebe Wang (phoebewang) ChangesRef.: https://cdrdv2.intel.com/v1/dl/getContent/828965 Patch is 35.87 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/123270.diff 16 Files Affected:
diff --git a/clang/include/clang/Basic/BuiltinsX86_64.td b/clang/include/clang/Basic/BuiltinsX86_64.td
index a6c6ef80eac212..4958265298d1bc 100644
--- a/clang/include/clang/Basic/BuiltinsX86_64.td
+++ b/clang/include/clang/Basic/BuiltinsX86_64.td
@@ -295,8 +295,8 @@ let Features = "amx-complex,amx-transpose", Attributes = [NoThrow] in {
let Features = "amx-avx512,avx10.2-512", Attributes = [NoThrow] in {
def tcvtrowd2ps_internal : X86Builtin<"_Vector<16, float>(unsigned short, unsigned short, _Vector<256, int>, unsigned int)">;
- def tcvtrowps2pbf16h_internal : X86Builtin<"_Vector<32, __bf16>(unsigned short, unsigned short, _Vector<256, int>, unsigned int)">;
- def tcvtrowps2pbf16l_internal : X86Builtin<"_Vector<32, __bf16>(unsigned short, unsigned short, _Vector<256, int>, unsigned int)">;
+ def tcvtrowps2bf16h_internal : X86Builtin<"_Vector<32, __bf16>(unsigned short, unsigned short, _Vector<256, int>, unsigned int)">;
+ def tcvtrowps2bf16l_internal : X86Builtin<"_Vector<32, __bf16>(unsigned short, unsigned short, _Vector<256, int>, unsigned int)">;
def tcvtrowps2phh_internal : X86Builtin<"_Vector<32, _Float16>(unsigned short, unsigned short, _Vector<256, int>, unsigned int)">;
def tcvtrowps2phl_internal : X86Builtin<"_Vector<32, _Float16>(unsigned short, unsigned short, _Vector<256, int>, unsigned int)">;
def tilemovrow_internal : X86Builtin<"_Vector<16, int>(unsigned short, unsigned short, _Vector<256, int>, unsigned int)">;
@@ -387,8 +387,8 @@ let Features = "amx-complex,amx-transpose", Attributes = [NoThrow] in {
let Features = "amx-avx512,avx10.2-512", Attributes = [NoThrow] in {
def tcvtrowd2ps : X86Builtin<"_Vector<16, float>(_Constant unsigned char, unsigned int)">;
- def tcvtrowps2pbf16h : X86Builtin<"_Vector<32, __bf16>(_Constant unsigned char, unsigned int)">;
- def tcvtrowps2pbf16l : X86Builtin<"_Vector<32, __bf16>(_Constant unsigned char, unsigned int)">;
+ def tcvtrowps2bf16h : X86Builtin<"_Vector<32, __bf16>(_Constant unsigned char, unsigned int)">;
+ def tcvtrowps2bf16l : X86Builtin<"_Vector<32, __bf16>(_Constant unsigned char, unsigned int)">;
def tcvtrowps2phh : X86Builtin<"_Vector<32, _Float16>(_Constant unsigned char, unsigned int)">;
def tcvtrowps2phl : X86Builtin<"_Vector<32, _Float16>(_Constant unsigned char, unsigned int)">;
def tilemovrow : X86Builtin<"_Vector<16, int>(_Constant unsigned char, unsigned int)">;
diff --git a/clang/lib/Headers/amxavx512intrin.h b/clang/lib/Headers/amxavx512intrin.h
index e4d77e503015af..17c8734dc963d5 100644
--- a/clang/lib/Headers/amxavx512intrin.h
+++ b/clang/lib/Headers/amxavx512intrin.h
@@ -60,7 +60,7 @@
/// \headerfile <x86intrin.h>
///
/// \code
-/// __m512i _tile_cvtrowps2pbf16h(__tile tsrc, unsigned int row);
+/// __m512i _tile_cvtrowps2bf16h(__tile tsrc, unsigned int row);
/// \endcode
///
/// \code{.operation}
@@ -80,14 +80,14 @@
/// zero_tileconfig_start()
/// \endcode
///
-/// This intrinsic corresponds to the \c TCVTROWPS2PBF16H instruction.
+/// This intrinsic corresponds to the \c TCVTROWPS2BF16H instruction.
///
/// \param tsrc
/// The source tile. Max size is 1024 Bytes.
/// \param row
/// The the row of the source tile.
-#define _tile_cvtrowps2pbf16h(tsrc, row) \
- __builtin_ia32_tcvtrowps2pbf16h(tsrc, row)
+#define _tile_cvtrowps2bf16h(tsrc, row) \
+ __builtin_ia32_tcvtrowps2bf16h(tsrc, row)
/// Moves a row from a tile register to a zmm destination register, converting
/// the fp32 source elements to bf16. It places the resulting bf16 elements
@@ -97,7 +97,7 @@
/// \headerfile <x86intrin.h>
///
/// \code
-/// __m512i _tile_cvtrowps2pbf16l(__tile tsrc, unsigned int row);
+/// __m512i _tile_cvtrowps2bf16l(__tile tsrc, unsigned int row);
/// \endcode
///
/// \code{.operation}
@@ -117,14 +117,14 @@
/// zero_tileconfig_start()
/// \endcode
///
-/// This intrinsic corresponds to the \c TCVTROWPS2PBF16L instruction.
+/// This intrinsic corresponds to the \c TCVTROWPS2BF16L instruction.
///
/// \param tsrc
/// The source tile. Max size is 1024 Bytes.
/// \param row
/// The the row of the source tile.
-#define _tile_cvtrowps2pbf16l(tsrc, row) \
- __builtin_ia32_tcvtrowps2pbf16l(tsrc, row)
+#define _tile_cvtrowps2bf16l(tsrc, row) \
+ __builtin_ia32_tcvtrowps2bf16l(tsrc, row)
/// Moves a row from a tile register to a zmm destination register, converting
/// the fp32 source elements to fp16. It places the resulting fp16 elements
@@ -238,15 +238,15 @@ static __inline__ __m512 __DEFAULT_FN_ATTRS_AVX512 _tile_cvtrowd2ps_internal(
}
static __inline__ __m512bh __DEFAULT_FN_ATTRS_AVX512
-_tile_cvtrowps2pbf16h_internal(unsigned short m, unsigned short n,
+_tile_cvtrowps2bf16h_internal(unsigned short m, unsigned short n,
_tile1024i src, unsigned u) {
- return __builtin_ia32_tcvtrowps2pbf16h_internal(m, n, src, u);
+ return __builtin_ia32_tcvtrowps2bf16h_internal(m, n, src, u);
}
static __inline__ __m512bh __DEFAULT_FN_ATTRS_AVX512
-_tile_cvtrowps2pbf16l_internal(unsigned short m, unsigned short n,
+_tile_cvtrowps2bf16l_internal(unsigned short m, unsigned short n,
_tile1024i src, unsigned u) {
- return __builtin_ia32_tcvtrowps2pbf16l_internal(m, n, src, u);
+ return __builtin_ia32_tcvtrowps2bf16l_internal(m, n, src, u);
}
static __inline__ __m512h __DEFAULT_FN_ATTRS_AVX512 _tile_cvtrowps2phh_internal(
@@ -290,7 +290,7 @@ static __m512 __tile_cvtrowd2ps(__tile1024i src0, unsigned src1) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the <c> TCVTROWPS2PBF16H </c> instruction.
+/// This intrinsic corresponds to the <c> TCVTROWPS2BF16H </c> instruction.
///
/// \param src0
/// The 1st source tile. Max size is 1024 Bytes.
@@ -299,8 +299,8 @@ static __m512 __tile_cvtrowd2ps(__tile1024i src0, unsigned src1) {
/// \returns
/// The destination v32bf16 data. Size is 64 Bytes.
__DEFAULT_FN_ATTRS_AVX512
-static __m512bh __tile_cvtrowps2pbf16h(__tile1024i src0, unsigned src1) {
- return _tile_cvtrowps2pbf16h_internal(src0.row, src0.col, src0.tile, src1);
+static __m512bh __tile_cvtrowps2bf16h(__tile1024i src0, unsigned src1) {
+ return _tile_cvtrowps2bf16h_internal(src0.row, src0.col, src0.tile, src1);
}
/// Move a row from a tile (src0) to a v32bf16 dst, converting the fp32 source
@@ -309,7 +309,7 @@ static __m512bh __tile_cvtrowps2pbf16h(__tile1024i src0, unsigned src1) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the <c> TCVTROWPS2PBF16L </c> instruction.
+/// This intrinsic corresponds to the <c> TCVTROWPS2BF16L </c> instruction.
///
/// \param src0
/// The 1st source tile. Max size is 1024 Bytes.
@@ -318,8 +318,8 @@ static __m512bh __tile_cvtrowps2pbf16h(__tile1024i src0, unsigned src1) {
/// \returns
/// The destination v32bf16 data. Size is 64 Bytes.
__DEFAULT_FN_ATTRS_AVX512
-static __m512bh __tile_cvtrowps2pbf16l(__tile1024i src0, unsigned src1) {
- return _tile_cvtrowps2pbf16l_internal(src0.row, src0.col, src0.tile, src1);
+static __m512bh __tile_cvtrowps2bf16l(__tile1024i src0, unsigned src1) {
+ return _tile_cvtrowps2bf16l_internal(src0.row, src0.col, src0.tile, src1);
}
/// Move a row from a tile (src0) to a v32fp16 dst, converting the fp32 source
diff --git a/clang/lib/Sema/SemaX86.cpp b/clang/lib/Sema/SemaX86.cpp
index 0b4b78c5b15dc5..fd1a6017712d20 100644
--- a/clang/lib/Sema/SemaX86.cpp
+++ b/clang/lib/Sema/SemaX86.cpp
@@ -641,8 +641,8 @@ bool SemaX86::CheckBuiltinTileArguments(unsigned BuiltinID, CallExpr *TheCall) {
case X86::BI__builtin_ia32_t2rpntlvwz1rs:
case X86::BI__builtin_ia32_t2rpntlvwz1rst1:
case X86::BI__builtin_ia32_t2rpntlvwz0rs:
- case X86::BI__builtin_ia32_tcvtrowps2pbf16h:
- case X86::BI__builtin_ia32_tcvtrowps2pbf16l:
+ case X86::BI__builtin_ia32_tcvtrowps2bf16h:
+ case X86::BI__builtin_ia32_tcvtrowps2bf16l:
case X86::BI__builtin_ia32_tcvtrowps2phh:
case X86::BI__builtin_ia32_tcvtrowps2phl:
case X86::BI__builtin_ia32_tcvtrowd2ps:
diff --git a/clang/test/CodeGen/X86/amx_avx512_api.c b/clang/test/CodeGen/X86/amx_avx512_api.c
index aea790d61268d3..fac41ea6c214f1 100644
--- a/clang/test/CodeGen/X86/amx_avx512_api.c
+++ b/clang/test/CodeGen/X86/amx_avx512_api.c
@@ -16,18 +16,18 @@ __m512 test_tile_cvtrowd2ps(__tile1024i a, unsigned b) {
return __tile_cvtrowd2ps(a, b);
}
-__m512bh test_tile_cvtrowps2pbf16h(__tile1024i a, unsigned b) {
- //CHECK-LABEL: @test_tile_cvtrowps2pbf16h
+__m512bh test_tile_cvtrowps2bf16h(__tile1024i a, unsigned b) {
+ //CHECK-LABEL: @test_tile_cvtrowps2bf16h
//CHECK-DAG: call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> {{%.*}})
- //CHECK-DAG: call <32 x bfloat> @llvm.x86.tcvtrowps2pbf16h.internal
- return __tile_cvtrowps2pbf16h(a, b);
+ //CHECK-DAG: call <32 x bfloat> @llvm.x86.tcvtrowps2bf16h.internal
+ return __tile_cvtrowps2bf16h(a, b);
}
-__m512bh test_tile_cvtrowps2pbf16l(__tile1024i a, unsigned b) {
- //CHECK-LABEL: @test_tile_cvtrowps2pbf16l
+__m512bh test_tile_cvtrowps2bf16l(__tile1024i a, unsigned b) {
+ //CHECK-LABEL: @test_tile_cvtrowps2bf16l
//CHECK-DAG: call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> {{%.*}})
- //CHECK-DAG: call <32 x bfloat> @llvm.x86.tcvtrowps2pbf16l.internal
- return __tile_cvtrowps2pbf16l(a, b);
+ //CHECK-DAG: call <32 x bfloat> @llvm.x86.tcvtrowps2bf16l.internal
+ return __tile_cvtrowps2bf16l(a, b);
}
__m512h test_tile_cvtrowps2phh(__tile1024i a, unsigned b) {
diff --git a/clang/test/CodeGen/X86/amxavx512-builtins.c b/clang/test/CodeGen/X86/amxavx512-builtins.c
index 172b5ae8f53081..0f203349b1d1ec 100644
--- a/clang/test/CodeGen/X86/amxavx512-builtins.c
+++ b/clang/test/CodeGen/X86/amxavx512-builtins.c
@@ -10,16 +10,16 @@ __m512 test_tile_cvtrowd2ps(unsigned int A) {
return _tile_cvtrowd2ps(1, A);
}
-__m512bh test_tile_cvtrowps2pbf16h(unsigned int A) {
- // CHECK-LABEL: @test_tile_cvtrowps2pbf16h(
- // CHECK: call <32 x bfloat> @llvm.x86.tcvtrowps2pbf16h(i8 1, i32 %{{.*}})
- return _tile_cvtrowps2pbf16h(1, A);
+__m512bh test_tile_cvtrowps2bf16h(unsigned int A) {
+ // CHECK-LABEL: @test_tile_cvtrowps2bf16h(
+ // CHECK: call <32 x bfloat> @llvm.x86.tcvtrowps2bf16h(i8 1, i32 %{{.*}})
+ return _tile_cvtrowps2bf16h(1, A);
}
-__m512bh test_tile_cvtrowps2pbf16l(unsigned int A) {
- // CHECK-LABEL: @test_tile_cvtrowps2pbf16l(
- // CHECK: call <32 x bfloat> @llvm.x86.tcvtrowps2pbf16l(i8 1, i32 %{{.*}})
- return _tile_cvtrowps2pbf16l(1, A);
+__m512bh test_tile_cvtrowps2bf16l(unsigned int A) {
+ // CHECK-LABEL: @test_tile_cvtrowps2bf16l(
+ // CHECK: call <32 x bfloat> @llvm.x86.tcvtrowps2bf16l(i8 1, i32 %{{.*}})
+ return _tile_cvtrowps2bf16l(1, A);
}
__m512h test_tile_cvtrowps2phh(unsigned int A) {
diff --git a/llvm/include/llvm/IR/IntrinsicsX86.td b/llvm/include/llvm/IR/IntrinsicsX86.td
index 42b211e0e1f75a..fb12949e10c7e5 100644
--- a/llvm/include/llvm/IR/IntrinsicsX86.td
+++ b/llvm/include/llvm/IR/IntrinsicsX86.td
@@ -5999,10 +5999,10 @@ let TargetPrefix = "x86" in {
def int_x86_tcvtrowd2ps : ClangBuiltin<"__builtin_ia32_tcvtrowd2ps">,
Intrinsic<[llvm_v16f32_ty], [llvm_i8_ty, llvm_i32_ty],
[ImmArg<ArgIndex<0>>]>;
- def int_x86_tcvtrowps2pbf16h : ClangBuiltin<"__builtin_ia32_tcvtrowps2pbf16h">,
+ def int_x86_tcvtrowps2bf16h : ClangBuiltin<"__builtin_ia32_tcvtrowps2bf16h">,
Intrinsic<[llvm_v32bf16_ty], [llvm_i8_ty, llvm_i32_ty],
[ImmArg<ArgIndex<0>>]>;
- def int_x86_tcvtrowps2pbf16l : ClangBuiltin<"__builtin_ia32_tcvtrowps2pbf16l">,
+ def int_x86_tcvtrowps2bf16l : ClangBuiltin<"__builtin_ia32_tcvtrowps2bf16l">,
Intrinsic<[llvm_v32bf16_ty], [llvm_i8_ty, llvm_i32_ty],
[ImmArg<ArgIndex<0>>]>;
def int_x86_tcvtrowps2phh : ClangBuiltin<"__builtin_ia32_tcvtrowps2phh">,
@@ -6181,13 +6181,13 @@ let TargetPrefix = "x86" in {
Intrinsic<[llvm_v16f32_ty],
[llvm_i16_ty, llvm_i16_ty, llvm_x86amx_ty, llvm_i32_ty],
[]>;
- def int_x86_tcvtrowps2pbf16h_internal :
- ClangBuiltin<"__builtin_ia32_tcvtrowps2pbf16h_internal">,
+ def int_x86_tcvtrowps2bf16h_internal :
+ ClangBuiltin<"__builtin_ia32_tcvtrowps2bf16h_internal">,
Intrinsic<[llvm_v32bf16_ty],
[llvm_i16_ty, llvm_i16_ty, llvm_x86amx_ty, llvm_i32_ty],
[]>;
- def int_x86_tcvtrowps2pbf16l_internal :
- ClangBuiltin<"__builtin_ia32_tcvtrowps2pbf16l_internal">,
+ def int_x86_tcvtrowps2bf16l_internal :
+ ClangBuiltin<"__builtin_ia32_tcvtrowps2bf16l_internal">,
Intrinsic<[llvm_v32bf16_ty],
[llvm_i16_ty, llvm_i16_ty, llvm_x86amx_ty, llvm_i32_ty],
[]>;
@@ -7893,4 +7893,4 @@ def int_x86_movrsdi : ClangBuiltin<"__builtin_ia32_movrsdi">,
[IntrReadMem]>;
def int_x86_prefetchrs : ClangBuiltin<"__builtin_ia32_prefetchrs">,
Intrinsic<[], [llvm_ptr_ty], []>;
-}
\ No newline at end of file
+}
diff --git a/llvm/lib/Target/X86/X86ExpandPseudo.cpp b/llvm/lib/Target/X86/X86ExpandPseudo.cpp
index fc8a0eaed140d0..5e75fb113a01d4 100644
--- a/llvm/lib/Target/X86/X86ExpandPseudo.cpp
+++ b/llvm/lib/Target/X86/X86ExpandPseudo.cpp
@@ -563,10 +563,10 @@ bool X86ExpandPseudo::expandMI(MachineBasicBlock &MBB,
case X86::PTILELOADDRST1V:
case X86::PTCVTROWD2PSrreV:
case X86::PTCVTROWD2PSrriV:
- case X86::PTCVTROWPS2PBF16HrreV:
- case X86::PTCVTROWPS2PBF16HrriV:
- case X86::PTCVTROWPS2PBF16LrreV:
- case X86::PTCVTROWPS2PBF16LrriV:
+ case X86::PTCVTROWPS2BF16HrreV:
+ case X86::PTCVTROWPS2BF16HrriV:
+ case X86::PTCVTROWPS2BF16LrreV:
+ case X86::PTCVTROWPS2BF16LrriV:
case X86::PTCVTROWPS2PHHrreV:
case X86::PTCVTROWPS2PHHrriV:
case X86::PTCVTROWPS2PHLrreV:
@@ -595,17 +595,17 @@ bool X86ExpandPseudo::expandMI(MachineBasicBlock &MBB,
case X86::PTCVTROWD2PSrriV:
Opc = X86::TCVTROWD2PSrri;
break;
- case X86::PTCVTROWPS2PBF16HrreV:
- Opc = X86::TCVTROWPS2PBF16Hrre;
+ case X86::PTCVTROWPS2BF16HrreV:
+ Opc = X86::TCVTROWPS2BF16Hrre;
break;
- case X86::PTCVTROWPS2PBF16HrriV:
- Opc = X86::TCVTROWPS2PBF16Hrri;
+ case X86::PTCVTROWPS2BF16HrriV:
+ Opc = X86::TCVTROWPS2BF16Hrri;
break;
- case X86::PTCVTROWPS2PBF16LrreV:
- Opc = X86::TCVTROWPS2PBF16Lrre;
+ case X86::PTCVTROWPS2BF16LrreV:
+ Opc = X86::TCVTROWPS2BF16Lrre;
break;
- case X86::PTCVTROWPS2PBF16LrriV:
- Opc = X86::TCVTROWPS2PBF16Lrri;
+ case X86::PTCVTROWPS2BF16LrriV:
+ Opc = X86::TCVTROWPS2BF16Lrri;
break;
case X86::PTCVTROWPS2PHHrreV:
Opc = X86::TCVTROWPS2PHHrre;
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 90e3e15b1fb46c..57b86d8d6a1c4d 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -37890,8 +37890,8 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
MI.eraseFromParent(); // The pseudo is gone now.
return BB;
}
- case X86::PTCVTROWPS2PBF16Hrri:
- case X86::PTCVTROWPS2PBF16Lrri:
+ case X86::PTCVTROWPS2BF16Hrri:
+ case X86::PTCVTROWPS2BF16Lrri:
case X86::PTCVTROWPS2PHHrri:
case X86::PTCVTROWPS2PHLrri:
case X86::PTCVTROWD2PSrri:
@@ -37904,14 +37904,14 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
case X86::PTCVTROWD2PSrri:
Opc = X86::TCVTROWD2PSrri;
break;
- case X86::PTCVTROWPS2PBF16Hrri:
- Opc = X86::TCVTROWPS2PBF16Hrri;
+ case X86::PTCVTROWPS2BF16Hrri:
+ Opc = X86::TCVTROWPS2BF16Hrri;
break;
case X86::PTCVTROWPS2PHHrri:
Opc = X86::TCVTROWPS2PHHrri;
break;
- case X86::PTCVTROWPS2PBF16Lrri:
- Opc = X86::TCVTROWPS2PBF16Lrri;
+ case X86::PTCVTROWPS2BF16Lrri:
+ Opc = X86::TCVTROWPS2BF16Lrri;
break;
case X86::PTCVTROWPS2PHLrri:
Opc = X86::TCVTROWPS2PHLrri;
@@ -37928,8 +37928,8 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
MI.eraseFromParent(); // The pseudo is gone now.
return BB;
}
- case X86::PTCVTROWPS2PBF16Hrre:
- case X86::PTCVTROWPS2PBF16Lrre:
+ case X86::PTCVTROWPS2BF16Hrre:
+ case X86::PTCVTROWPS2BF16Lrre:
case X86::PTCVTROWPS2PHHrre:
case X86::PTCVTROWPS2PHLrre:
case X86::PTCVTROWD2PSrre:
@@ -37942,11 +37942,11 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
case X86::PTCVTROWD2PSrre:
Opc = X86::TCVTROWD2PSrre;
break;
- case X86::PTCVTROWPS2PBF16Hrre:
- Opc = X86::TCVTROWPS2PBF16Hrre;
+ case X86::PTCVTROWPS2BF16Hrre:
+ Opc = X86::TCVTROWPS2BF16Hrre;
break;
- case X86::PTCVTROWPS2PBF16Lrre:
- Opc = X86::TCVTROWPS2PBF16Lrre;
+ case X86::PTCVTROWPS2BF16Lrre:
+ Opc = X86::TCVTROWPS2BF16Lrre;
break;
case X86::PTCVTROWPS2PHHrre:
Opc = X86::TCVTROWPS2PHHrre;
diff --git a/llvm/lib/Target/X86/X86InstrAMX.td b/llvm/lib/Target/X86/X86InstrAMX.td
index a055ba91d3e171..d3592733a4b28b 100644
--- a/llvm/lib/Target/X86/X86InstrAMX.td
+++ b/llvm/lib/Target/X86/X86InstrAMX.td
@@ -590,26 +590,26 @@ let Predicates = [HasAMXAVX512, HasAVX10_2_512, In64BitMode] in {
[(set VR512: $dst,
(int_x86_tcvtrowd2ps_internal GR16:$src1, GR16:$src2,
TILE:$src3, GR32:$src4))]>;
- def PTCVTROWPS2PBF16HrriV : PseudoI<(outs VR512:$dst),
- (ins GR16:$src1, GR16:$src2, TILE:$src3, i32u8imm:$src4),
- [(set VR512: $dst,
- (int_x86_tcvtrowps2pbf16h_internal GR16:$src1, GR16:$src2,
- TILE:$src3, imm:$src4))]>;
- def PTCVTROWPS2PBF16HrreV : PseudoI<(outs VR512:$dst),
- (ins GR16:$src1, GR16:$src2, TILE:$src3, GR32:$src4),
- [(set VR512: $dst,
- (int_x86_tcvtrowps2pbf16h_internal GR16:$src1, GR16:$src2,
- TILE:$src3, GR32:$src4))]>;
- def PTCVTROWPS2PBF16LrriV : PseudoI<(outs VR512:$dst),
- (ins GR16:$src1, GR16:$src2, TILE:$src3, i32u8imm:$src4),
- [(set VR512: $dst,
- (int_x86_tcvtrowps2pbf16l_internal GR16:$src1, GR16:$src2,
- TILE:$src3, imm:$src4))]>;
- def PTCVTROWPS2PBF16LrreV : PseudoI<(outs VR512:$dst),
- (ins GR16:$src1, GR16:$src2, TILE:$src3, GR32:$src4),
- [(set VR512: $dst,
- (int_x86_tcvtrowps2pbf16l_internal GR16:$src1, GR16:$src2,
- TILE:$src3, GR32:$src4))]>;
+ def PTCVTROWPS2BF16HrriV : PseudoI<(outs VR512:$dst),
+ (ins GR16:$src1, GR16:$src2, TILE:$src3, i32u8imm:$src4),
+ [(set VR512: $dst,
+ (int_x86_tcvtrowps2bf16h_internal GR16:$src1, GR16:$src2,
+ TILE:$src3, imm:$src4))]>;
+ def PTCVTROWPS2BF16HrreV : PseudoI<(outs VR512:$dst),
+ (ins GR16:$src1, GR16:$src2, TILE:$src3, GR32:$src4),
+ [(set VR512: $dst,
+ (int_x86_tcvtrowps2bf16h_internal GR16:$src1, GR16:$src2,
+ TILE:$src3, GR32:$src4))]>;
+ def PTCVTROWPS2BF16LrriV : PseudoI<(outs VR512:$dst),
+ (ins GR16:$src1, GR16:$src2, TILE:$src3, i32u8imm:$src4),
+ [(set VR512: $dst,
+ (int_x86_tcvtrowps2bf16l_internal GR16:$src1, GR16:$src2,
+ TILE:$src3, imm:$src4))]>;
+ def PTCVTROWPS2BF...
[truncated]
|
You can test this locally with the following command:git-clang-format --diff a761e26b2364ea457b79b9a4bea6d792e4913d24 ebab1ea66e400f84eb0dca846187ea5a365d1c14 --extensions c,h,cpp -- clang/lib/Headers/amxavx512intrin.h clang/lib/Sema/SemaX86.cpp clang/test/CodeGen/X86/amx_avx512_api.c clang/test/CodeGen/X86/amxavx512-builtins.c llvm/lib/Target/X86/X86ExpandPseudo.cpp llvm/lib/Target/X86/X86ISelLowering.cpp llvm/lib/Target/X86/X86LowerAMXType.cpp llvm/lib/Target/X86/X86PreTileConfig.cppView the diff from clang-format here.diff --git a/clang/lib/Headers/amxavx512intrin.h b/clang/lib/Headers/amxavx512intrin.h
index a158983482..850b4c467e 100644
--- a/clang/lib/Headers/amxavx512intrin.h
+++ b/clang/lib/Headers/amxavx512intrin.h
@@ -73,7 +73,8 @@
/// dst.dword[i] := 0
/// ELSE
/// dst.word[2*i+0] := 0
-/// dst.bf16[2*i+1] := CONVERT_FP32_TO_BF16(tsrc.row[row_index].fp32[row_chunk/4+i], RNE)
+/// dst.bf16[2*i+1] :=
+/// CONVERT_FP32_TO_BF16(tsrc.row[row_index].fp32[row_chunk/4+i], RNE)
/// FI
/// ENDFOR
/// dst[MAX_VL-1:VL] := 0
@@ -110,7 +111,8 @@
/// dst.dword[i] := 0
/// ELSE
/// dst.word[2*i+1] := 0
-/// dst.bf16[2*i+0] := CONVERT_FP32_TO_BF16(tsrc.row[row_index].fp32[row_chunk/4+i], RNE)
+/// dst.bf16[2*i+0] :=
+/// CONVERT_FP32_TO_BF16(tsrc.row[row_index].fp32[row_chunk/4+i], RNE)
/// FI
/// ENDFOR
/// dst[MAX_VL-1:VL] := 0
|
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/73/builds/11903 Here is the relevant piece of the build log for the reference |
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Ref.: https://cdrdv2.intel.com/v1/dl/getContent/828965