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[AMDGPU][NewPM] Port AMDGPUReserveWWMRegs to NPM #123722

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Merged
merged 3 commits into from
Mar 10, 2025
Merged

[AMDGPU][NewPM] Port AMDGPUReserveWWMRegs to NPM #123722

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[AMDGPU][NewPM] Port AMDGPUReserveWWMRegs to NPM
optimisan Jan 21, 2025
9c24b02
add is required
optimisan Mar 10, 2025
7d16d38
add todo
optimisan Mar 10, 2025
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4 changes: 2 additions & 2 deletions llvm/lib/Target/AMDGPU/AMDGPU.h
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Original file line number Diff line number Diff line change
Expand Up @@ -156,8 +156,8 @@ struct AMDGPULowerBufferFatPointersPass
const TargetMachine &TM;
};

void initializeAMDGPUReserveWWMRegsPass(PassRegistry &);
extern char &AMDGPUReserveWWMRegsID;
void initializeAMDGPUReserveWWMRegsLegacyPass(PassRegistry &);
extern char &AMDGPUReserveWWMRegsLegacyID;

void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &);
extern char &AMDGPURewriteOutArgumentsID;
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1 change: 1 addition & 0 deletions llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
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Expand Up @@ -99,6 +99,7 @@ FUNCTION_PASS_WITH_PARAMS(
MACHINE_FUNCTION_PASS("amdgpu-insert-delay-alu", AMDGPUInsertDelayAluPass())
MACHINE_FUNCTION_PASS("amdgpu-isel", AMDGPUISelDAGToDAGPass(*this))
MACHINE_FUNCTION_PASS("amdgpu-pre-ra-long-branch-reg", GCNPreRALongBranchRegPass())
MACHINE_FUNCTION_PASS("amdgpu-reserve-wwm-regs", AMDGPUReserveWWMRegsPass())
MACHINE_FUNCTION_PASS("amdgpu-rewrite-partial-reg-uses", GCNRewritePartialRegUsesPass())
MACHINE_FUNCTION_PASS("amdgpu-pre-ra-optimizations", GCNPreRAOptimizationsPass())
MACHINE_FUNCTION_PASS("amdgpu-nsa-reassign", GCNNSAReassignPass())
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33 changes: 26 additions & 7 deletions llvm/lib/Target/AMDGPU/AMDGPUReserveWWMRegs.cpp
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Expand Up @@ -14,6 +14,7 @@
//
//===----------------------------------------------------------------------===//

#include "AMDGPUReserveWWMRegs.h"
#include "AMDGPU.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "SIMachineFunctionInfo.h"
Expand All @@ -27,12 +28,12 @@ using namespace llvm;

namespace {

class AMDGPUReserveWWMRegs : public MachineFunctionPass {
class AMDGPUReserveWWMRegsLegacy : public MachineFunctionPass {
public:
static char ID;

AMDGPUReserveWWMRegs() : MachineFunctionPass(ID) {
initializeAMDGPUReserveWWMRegsPass(*PassRegistry::getPassRegistry());
AMDGPUReserveWWMRegsLegacy() : MachineFunctionPass(ID) {
initializeAMDGPUReserveWWMRegsLegacyPass(*PassRegistry::getPassRegistry());
}

bool runOnMachineFunction(MachineFunction &MF) override;
Expand All @@ -47,16 +48,34 @@ class AMDGPUReserveWWMRegs : public MachineFunctionPass {
}
};

class AMDGPUReserveWWMRegs {
public:
bool run(MachineFunction &MF);
};

} // End anonymous namespace.

INITIALIZE_PASS(AMDGPUReserveWWMRegs, DEBUG_TYPE,
INITIALIZE_PASS(AMDGPUReserveWWMRegsLegacy, DEBUG_TYPE,
"AMDGPU Reserve WWM Registers", false, false)

char AMDGPUReserveWWMRegs::ID = 0;
char AMDGPUReserveWWMRegsLegacy::ID = 0;

char &llvm::AMDGPUReserveWWMRegsLegacyID = AMDGPUReserveWWMRegsLegacy::ID;

char &llvm::AMDGPUReserveWWMRegsID = AMDGPUReserveWWMRegs::ID;
bool AMDGPUReserveWWMRegsLegacy::runOnMachineFunction(MachineFunction &MF) {
return AMDGPUReserveWWMRegs().run(MF);
}

PreservedAnalyses
AMDGPUReserveWWMRegsPass::run(MachineFunction &MF,
MachineFunctionAnalysisManager &) {
AMDGPUReserveWWMRegs().run(MF);
// TODO: This should abandon RegisterClassInfo once it is turned into an
// analysis.
return PreservedAnalyses::all();
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There's an open PR to treat RegisterClassInfo as an analysis this will not preserve

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Can you add a fixme to do something about RegisterClassInfo

}

bool AMDGPUReserveWWMRegs::runOnMachineFunction(MachineFunction &MF) {
bool AMDGPUReserveWWMRegs::run(MachineFunction &MF) {
SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();

bool Changed = false;
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24 changes: 24 additions & 0 deletions llvm/lib/Target/AMDGPU/AMDGPUReserveWWMRegs.h
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@@ -0,0 +1,24 @@
//===- AMDGPUReserveWWMRegs.h -----------------------------------*- C++- *-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//

#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPURESERVEWWMREGS_H
#define LLVM_LIB_TARGET_AMDGPU_AMDGPURESERVEWWMREGS_H

#include "llvm/CodeGen/MachinePassManager.h"

namespace llvm {
class AMDGPUReserveWWMRegsPass
: public PassInfoMixin<AMDGPUReserveWWMRegsPass> {
public:
PreservedAnalyses run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM);
static bool isRequired() { return true; }
};
} // namespace llvm

#endif // LLVM_LIB_TARGET_AMDGPU_AMDGPURESERVEWWMREGS_H
7 changes: 4 additions & 3 deletions llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
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Expand Up @@ -25,6 +25,7 @@
#include "AMDGPUOpenCLEnqueuedBlockLowering.h"
#include "AMDGPUPerfHintAnalysis.h"
#include "AMDGPURemoveIncompatibleFunctions.h"
#include "AMDGPUReserveWWMRegs.h"
#include "AMDGPUSplitModule.h"
#include "AMDGPUTargetObjectFile.h"
#include "AMDGPUTargetTransformInfo.h"
Expand Down Expand Up @@ -528,7 +529,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
initializeAMDGPURemoveIncompatibleFunctionsLegacyPass(*PR);
initializeAMDGPULowerModuleLDSLegacyPass(*PR);
initializeAMDGPULowerBufferFatPointersPass(*PR);
initializeAMDGPUReserveWWMRegsPass(*PR);
initializeAMDGPUReserveWWMRegsLegacyPass(*PR);
initializeAMDGPURewriteOutArgumentsPass(*PR);
initializeAMDGPURewriteUndefForPHILegacyPass(*PR);
initializeAMDGPUUnifyMetadataPass(*PR);
Expand Down Expand Up @@ -1599,7 +1600,7 @@ bool GCNPassConfig::addRegAssignAndRewriteFast() {
addPass(createWWMRegAllocPass(false));

addPass(&SILowerWWMCopiesLegacyID);
addPass(&AMDGPUReserveWWMRegsID);
addPass(&AMDGPUReserveWWMRegsLegacyID);

// For allocating per-thread VGPRs.
addPass(createVGPRAllocPass(false));
Expand Down Expand Up @@ -1636,7 +1637,7 @@ bool GCNPassConfig::addRegAssignAndRewriteOptimized() {
addPass(createWWMRegAllocPass(true));
addPass(&SILowerWWMCopiesLegacyID);
addPass(createVirtRegRewriter(false));
addPass(&AMDGPUReserveWWMRegsID);
addPass(&AMDGPUReserveWWMRegsLegacyID);

// For allocating per-thread VGPRs.
addPass(createVGPRAllocPass(true));
Expand Down