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[AArch64] Codegen for new SCVTF/UCVTF variants (FEAT_FPRCVT) #123767

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Merged
merged 3 commits into from
Feb 6, 2025
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[AArch64] Codegen for new SCVTF/UCVTF variants (FEAT_FPRCVT) #123767

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5812fcd
[AArch64] Codegen for new SCVTF/UCVTF variants (FEAT_FPRCVT)
virginia-cangelosi Jan 21, 2025
8f1e439
fixup! Address review comments
virginia-cangelosi Jan 30, 2025
ebafcb4
Add more tests to fprcvt-cvtf.ll
virginia-cangelosi Feb 3, 2025
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10 changes: 9 additions & 1 deletion llvm/lib/Target/AArch64/AArch64InstrFormats.td
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Original file line number Diff line number Diff line change
Expand Up @@ -5511,6 +5511,15 @@ multiclass IntegerToFPSIMDScalar<bits<2> rmode, bits<3> opcode, string asm, SDPa
let Inst{31} = 1; // 64-bit FPR flag
let Inst{23-22} = 0b00; // 32-bit FPR flag
}

def : Pat<(f16 (node (i32 (extractelt (v4i32 V128:$Rn), (i64 0))))),
(!cast<Instruction>(NAME # HSr) (EXTRACT_SUBREG $Rn, ssub))>;
def : Pat<(f64 (node (i32 (extractelt (v4i32 V128:$Rn), (i64 0))))),
(!cast<Instruction>(NAME # DSr) (EXTRACT_SUBREG $Rn, ssub))>;
def : Pat<(f16 (node (i64 (extractelt (v2i64 V128:$Rn), (i64 0))))),
(!cast<Instruction>(NAME # HDr) (EXTRACT_SUBREG $Rn, dsub))>;
def : Pat<(f32 (node (i64 (extractelt (v2i64 V128:$Rn), (i64 0))))),
(!cast<Instruction>(NAME # SDr) (EXTRACT_SUBREG $Rn, dsub))>;
}

//---
Expand Down Expand Up @@ -13270,4 +13279,3 @@ multiclass SIMDThreeSameVectorFP8MatrixMul<string asm>{
let Predicates = [HasNEON, HasF8F32MM];
}
}

4 changes: 2 additions & 2 deletions llvm/lib/Target/AArch64/AArch64InstrInfo.td
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Expand Up @@ -5068,8 +5068,8 @@ defm SCVTF : IntegerToFP<0b00, 0b010, "scvtf", any_sint_to_fp>;
defm UCVTF : IntegerToFP<0b00, 0b011, "ucvtf", any_uint_to_fp>;

let Predicates = [HasNEON, HasFPRCVT] in {
defm SCVTF : IntegerToFPSIMDScalar<0b11, 0b100, "scvtf">;
defm UCVTF : IntegerToFPSIMDScalar<0b11, 0b101, "ucvtf">;
defm SCVTF : IntegerToFPSIMDScalar<0b11, 0b100, "scvtf", any_sint_to_fp>;
defm UCVTF : IntegerToFPSIMDScalar<0b11, 0b101, "ucvtf", any_uint_to_fp>;
}

def : Pat<(f16 (fdiv (f16 (any_sint_to_fp (i32 GPR32:$Rn))), fixedpoint_f16_i32:$scale)),
Expand Down
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