[RISCV] Add P550 scheduler model. #124639
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P550 falls between P450 and P650. It has 1 additional FEX pipe over P450. Mul and cpop latency are 3 instead of 2. I've set the MicroOpBufferSize to 96 instead of 56 based on the ROB size measurement from https://chipsandcheese.com/p/inside-sifives-p550-microarchitecture I believe we set this value too low for P450 and P650 and should update them in a separate PR.
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@llvm/pr-subscribers-backend-risc-v Author: Craig Topper (topperc) ChangesP550 falls between P450 and P650. It has 1 additional FEX pipe over P450. Mul and cpop latency are 3 instead of 2. I've set the MicroOpBufferSize to 96 instead of 56 based on the ROB size measurement from https://chipsandcheese.com/p/inside-sifives-p550-microarchitecture I believe we set this value too low for P450 and P650 and should update them in a separate PR. Patch is 35.45 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/124639.diff 6 Files Affected:
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index 4e0c64a5ca2c6f..87c07c3cd505fd 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -50,6 +50,7 @@ include "RISCVSchedMIPSP8700.td"
include "RISCVSchedRocket.td"
include "RISCVSchedSiFive7.td"
include "RISCVSchedSiFiveP400.td"
+include "RISCVSchedSiFiveP500.td"
include "RISCVSchedSiFiveP600.td"
include "RISCVSchedSyntacoreSCR1.td"
include "RISCVSchedSyntacoreSCR345.td"
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 6dfed7ddeb9f63..28b13f74c29913 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -327,7 +327,7 @@ defvar SiFiveP500TuneFeatures = [TuneNoDefaultUnroll,
TuneAUIPCADDIFusion,
TunePostRAScheduler];
-def SIFIVE_P550 : RISCVProcessorModel<"sifive-p550", NoSchedModel,
+def SIFIVE_P550 : RISCVProcessorModel<"sifive-p550", SiFiveP500Model,
[Feature64Bit,
FeatureStdExtI,
FeatureStdExtZifencei,
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td
new file mode 100644
index 00000000000000..32cfa701c4fdb8
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td
@@ -0,0 +1,361 @@
+//==- RISCVSchedSiFiveP500.td - SiFiveP500 Scheduling Defs ---*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+
+def SiFiveP500Model : SchedMachineModel {
+ let IssueWidth = 3; // 3 micro-ops are dispatched per cycle.
+ let MicroOpBufferSize = 96; // Max micro-ops that can be buffered.
+ let LoadLatency = 4; // Cycles for loads to access the cache.
+ let MispredictPenalty = 9; // Extra cycles for a mispredicted branch.
+ let CompleteModel = false;
+}
+
+// The SiFiveP500 microarchitecure has 7 pipelines:
+// Three pipelines for integer operations.
+// Two pipelines for FPU operations.
+// One pipeline for Load operations.
+// One pipeline for Store operations.
+let SchedModel = SiFiveP500Model in {
+
+def SiFiveP500IEXQ0 : ProcResource<1>;
+def SiFiveP500IEXQ1 : ProcResource<1>;
+def SiFiveP500IEXQ2 : ProcResource<1>;
+def SiFiveP500FEXQ0 : ProcResource<1>;
+def SiFiveP500FEXQ1 : ProcResource<1>;
+def SiFiveP500Load : ProcResource<1>;
+def SiFiveP500Store : ProcResource<1>;
+
+def SiFiveP500IntArith : ProcResGroup<[SiFiveP500IEXQ0, SiFiveP500IEXQ1, SiFiveP500IEXQ2]>;
+defvar SiFiveP500Branch = SiFiveP500IEXQ0;
+defvar SiFiveP500SYS = SiFiveP500IEXQ1;
+defvar SiFiveP500CMOV = SiFiveP500IEXQ1;
+defvar SiFiveP500MulI2F = SiFiveP500IEXQ2;
+def SiFiveP500Div : ProcResource<1>;
+
+def SiFiveP500FloatArith : ProcResGroup<[SiFiveP500FEXQ0, SiFiveP500FEXQ1]>;
+defvar SiFiveP500F2I = SiFiveP500FEXQ0;
+def SiFiveP500FloatDiv : ProcResource<1>;
+
+let Latency = 1 in {
+// Integer arithmetic and logic
+def : WriteRes<WriteIALU, [SiFiveP500IntArith]>;
+def : WriteRes<WriteIALU32, [SiFiveP500IntArith]>;
+def : WriteRes<WriteShiftImm, [SiFiveP500IntArith]>;
+def : WriteRes<WriteShiftImm32, [SiFiveP500IntArith]>;
+def : WriteRes<WriteShiftReg, [SiFiveP500IntArith]>;
+def : WriteRes<WriteShiftReg32, [SiFiveP500IntArith]>;
+// Branching
+def : WriteRes<WriteJmp, [SiFiveP500Branch]>;
+def : WriteRes<WriteJal, [SiFiveP500Branch]>;
+def : WriteRes<WriteJalr, [SiFiveP500Branch]>;
+}
+
+// CMOV
+def P500WriteCMOV : SchedWriteRes<[SiFiveP500Branch, SiFiveP500CMOV]> {
+ let Latency = 2;
+ let NumMicroOps = 2;
+}
+def : InstRW<[P500WriteCMOV], (instrs PseudoCCMOVGPRNoX0)>;
+
+let Latency = 3 in {
+// Integer multiplication
+def : WriteRes<WriteIMul, [SiFiveP500MulI2F]>;
+def : WriteRes<WriteIMul32, [SiFiveP500MulI2F]>;
+// cpop[w] look exactly like multiply.
+def : WriteRes<WriteCPOP, [SiFiveP500MulI2F]>;
+def : WriteRes<WriteCPOP32, [SiFiveP500MulI2F]>;
+}
+
+// Integer division
+def : WriteRes<WriteIDiv, [SiFiveP500MulI2F, SiFiveP500Div]> {
+ let Latency = 35;
+ let ReleaseAtCycles = [1, 34];
+}
+def : WriteRes<WriteIDiv32, [SiFiveP500MulI2F, SiFiveP500Div]> {
+ let Latency = 20;
+ let ReleaseAtCycles = [1, 19];
+}
+
+// Integer remainder
+def : WriteRes<WriteIRem, [SiFiveP500MulI2F, SiFiveP500Div]> {
+ let Latency = 35;
+ let ReleaseAtCycles = [1, 34];
+}
+def : WriteRes<WriteIRem32, [SiFiveP500MulI2F, SiFiveP500Div]> {
+ let Latency = 20;
+ let ReleaseAtCycles = [1, 19];
+}
+
+let Latency = 1 in {
+// Bitmanip
+def : WriteRes<WriteRotateImm, [SiFiveP500IntArith]>;
+def : WriteRes<WriteRotateImm32, [SiFiveP500IntArith]>;
+def : WriteRes<WriteRotateReg, [SiFiveP500IntArith]>;
+def : WriteRes<WriteRotateReg32, [SiFiveP500IntArith]>;
+
+def : WriteRes<WriteCLZ, [SiFiveP500IntArith]>;
+def : WriteRes<WriteCLZ32, [SiFiveP500IntArith]>;
+def : WriteRes<WriteCTZ, [SiFiveP500IntArith]>;
+def : WriteRes<WriteCTZ32, [SiFiveP500IntArith]>;
+
+def : WriteRes<WriteORCB, [SiFiveP500IntArith]>;
+def : WriteRes<WriteIMinMax, [SiFiveP500IntArith]>;
+
+def : WriteRes<WriteREV8, [SiFiveP500IntArith]>;
+
+def : WriteRes<WriteSHXADD, [SiFiveP500IntArith]>;
+def : WriteRes<WriteSHXADD32, [SiFiveP500IntArith]>;
+}
+
+// Memory
+let Latency = 1 in {
+def : WriteRes<WriteSTB, [SiFiveP500Store]>;
+def : WriteRes<WriteSTH, [SiFiveP500Store]>;
+def : WriteRes<WriteSTW, [SiFiveP500Store]>;
+def : WriteRes<WriteSTD, [SiFiveP500Store]>;
+def : WriteRes<WriteFST16, [SiFiveP500Store]>;
+def : WriteRes<WriteFST32, [SiFiveP500Store]>;
+def : WriteRes<WriteFST64, [SiFiveP500Store]>;
+}
+let Latency = 4 in {
+def : WriteRes<WriteLDB, [SiFiveP500Load]>;
+def : WriteRes<WriteLDH, [SiFiveP500Load]>;
+}
+let Latency = 4 in {
+def : WriteRes<WriteLDW, [SiFiveP500Load]>;
+def : WriteRes<WriteLDD, [SiFiveP500Load]>;
+}
+
+let Latency = 6 in {
+def : WriteRes<WriteFLD16, [SiFiveP500Load]>;
+def : WriteRes<WriteFLD32, [SiFiveP500Load]>;
+def : WriteRes<WriteFLD64, [SiFiveP500Load]>;
+}
+
+// Atomic memory
+let Latency = 3 in {
+def : WriteRes<WriteAtomicSTW, [SiFiveP500Store]>;
+def : WriteRes<WriteAtomicSTD, [SiFiveP500Store]>;
+def : WriteRes<WriteAtomicW, [SiFiveP500Load]>;
+def : WriteRes<WriteAtomicD, [SiFiveP500Load]>;
+def : WriteRes<WriteAtomicLDW, [SiFiveP500Load]>;
+def : WriteRes<WriteAtomicLDD, [SiFiveP500Load]>;
+}
+
+// Floating point
+let Latency = 4 in {
+def : WriteRes<WriteFAdd16, [SiFiveP500FloatArith]>;
+def : WriteRes<WriteFAdd32, [SiFiveP500FloatArith]>;
+def : WriteRes<WriteFAdd64, [SiFiveP500FloatArith]>;
+
+def : WriteRes<WriteFMul16, [SiFiveP500FloatArith]>;
+def : WriteRes<WriteFMul32, [SiFiveP500FloatArith]>;
+def : WriteRes<WriteFMul64, [SiFiveP500FloatArith]>;
+
+def : WriteRes<WriteFMA16, [SiFiveP500FloatArith]>;
+def : WriteRes<WriteFMA32, [SiFiveP500FloatArith]>;
+def : WriteRes<WriteFMA64, [SiFiveP500FloatArith]>;
+}
+
+let Latency = 2 in {
+def : WriteRes<WriteFSGNJ16, [SiFiveP500FloatArith]>;
+def : WriteRes<WriteFSGNJ32, [SiFiveP500FloatArith]>;
+def : WriteRes<WriteFSGNJ64, [SiFiveP500FloatArith]>;
+
+def : WriteRes<WriteFMinMax16, [SiFiveP500FloatArith]>;
+def : WriteRes<WriteFMinMax32, [SiFiveP500FloatArith]>;
+def : WriteRes<WriteFMinMax64, [SiFiveP500FloatArith]>;
+}
+
+// Half precision.
+def : WriteRes<WriteFDiv16, [SiFiveP500FEXQ1, SiFiveP500FloatDiv]> {
+ let Latency = 19;
+ let ReleaseAtCycles = [1, 18];
+}
+def : WriteRes<WriteFSqrt16, [SiFiveP500FEXQ1, SiFiveP500FloatDiv]> {
+ let Latency = 18;
+ let ReleaseAtCycles = [1, 17];
+}
+
+// Single precision.
+def : WriteRes<WriteFDiv32, [SiFiveP500FEXQ1, SiFiveP500FloatDiv]> {
+ let Latency = 19;
+ let ReleaseAtCycles = [1, 18];
+}
+def : WriteRes<WriteFSqrt32, [SiFiveP500FEXQ1, SiFiveP500FloatDiv]> {
+ let Latency = 18;
+ let ReleaseAtCycles = [1, 17];
+}
+
+// Double precision
+def : WriteRes<WriteFDiv64, [SiFiveP500FEXQ1, SiFiveP500FloatDiv]> {
+ let Latency = 33;
+ let ReleaseAtCycles = [1, 32];
+}
+def : WriteRes<WriteFSqrt64, [SiFiveP500FEXQ1, SiFiveP500FloatDiv]> {
+ let Latency = 33;
+ let ReleaseAtCycles = [1, 32];
+}
+
+// Conversions
+let Latency = 2 in {
+def : WriteRes<WriteFCvtI32ToF16, [SiFiveP500MulI2F]>;
+def : WriteRes<WriteFCvtI32ToF32, [SiFiveP500MulI2F]>;
+def : WriteRes<WriteFCvtI32ToF64, [SiFiveP500MulI2F]>;
+def : WriteRes<WriteFCvtI64ToF16, [SiFiveP500MulI2F]>;
+def : WriteRes<WriteFCvtI64ToF32, [SiFiveP500MulI2F]>;
+def : WriteRes<WriteFCvtI64ToF64, [SiFiveP500MulI2F]>;
+def : WriteRes<WriteFCvtF16ToI32, [SiFiveP500F2I]>;
+def : WriteRes<WriteFCvtF16ToI64, [SiFiveP500F2I]>;
+def : WriteRes<WriteFCvtF16ToF32, [SiFiveP500FloatArith]>;
+def : WriteRes<WriteFCvtF16ToF64, [SiFiveP500FloatArith]>;
+def : WriteRes<WriteFCvtF32ToI32, [SiFiveP500F2I]>;
+def : WriteRes<WriteFCvtF32ToI64, [SiFiveP500F2I]>;
+def : WriteRes<WriteFCvtF32ToF16, [SiFiveP500FloatArith]>;
+def : WriteRes<WriteFCvtF32ToF64, [SiFiveP500FloatArith]>;
+def : WriteRes<WriteFCvtF64ToI32, [SiFiveP500F2I]>;
+def : WriteRes<WriteFCvtF64ToI64, [SiFiveP500F2I]>;
+def : WriteRes<WriteFCvtF64ToF16, [SiFiveP500FloatArith]>;
+def : WriteRes<WriteFCvtF64ToF32, [SiFiveP500FloatArith]>;
+
+def : WriteRes<WriteFClass16, [SiFiveP500F2I]>;
+def : WriteRes<WriteFClass32, [SiFiveP500F2I]>;
+def : WriteRes<WriteFClass64, [SiFiveP500F2I]>;
+def : WriteRes<WriteFCmp16, [SiFiveP500F2I]>;
+def : WriteRes<WriteFCmp32, [SiFiveP500F2I]>;
+def : WriteRes<WriteFCmp64, [SiFiveP500F2I]>;
+def : WriteRes<WriteFMovI16ToF16, [SiFiveP500MulI2F]>;
+def : WriteRes<WriteFMovF16ToI16, [SiFiveP500F2I]>;
+def : WriteRes<WriteFMovI32ToF32, [SiFiveP500MulI2F]>;
+def : WriteRes<WriteFMovF32ToI32, [SiFiveP500F2I]>;
+def : WriteRes<WriteFMovI64ToF64, [SiFiveP500MulI2F]>;
+def : WriteRes<WriteFMovF64ToI64, [SiFiveP500F2I]>;
+}
+
+// Others
+def : WriteRes<WriteCSR, [SiFiveP500SYS]>;
+def : WriteRes<WriteNop, []>;
+
+// FIXME: This could be better modeled by looking at the regclasses of the operands.
+def : InstRW<[WriteIALU, ReadIALU], (instrs COPY)>;
+
+//===----------------------------------------------------------------------===//
+// Bypass and advance
+def : ReadAdvance<ReadJmp, 0>;
+def : ReadAdvance<ReadJalr, 0>;
+def : ReadAdvance<ReadCSR, 0>;
+def : ReadAdvance<ReadStoreData, 0>;
+def : ReadAdvance<ReadMemBase, 0>;
+def : ReadAdvance<ReadIALU, 0>;
+def : ReadAdvance<ReadIALU32, 0>;
+def : ReadAdvance<ReadShiftImm, 0>;
+def : ReadAdvance<ReadShiftImm32, 0>;
+def : ReadAdvance<ReadShiftReg, 0>;
+def : ReadAdvance<ReadShiftReg32, 0>;
+def : ReadAdvance<ReadIDiv, 0>;
+def : ReadAdvance<ReadIDiv32, 0>;
+def : ReadAdvance<ReadIRem, 0>;
+def : ReadAdvance<ReadIRem32, 0>;
+def : ReadAdvance<ReadIMul, 0>;
+def : ReadAdvance<ReadIMul32, 0>;
+def : ReadAdvance<ReadAtomicWA, 0>;
+def : ReadAdvance<ReadAtomicWD, 0>;
+def : ReadAdvance<ReadAtomicDA, 0>;
+def : ReadAdvance<ReadAtomicDD, 0>;
+def : ReadAdvance<ReadAtomicLDW, 0>;
+def : ReadAdvance<ReadAtomicLDD, 0>;
+def : ReadAdvance<ReadAtomicSTW, 0>;
+def : ReadAdvance<ReadAtomicSTD, 0>;
+def : ReadAdvance<ReadFStoreData, 0>;
+def : ReadAdvance<ReadFMemBase, 0>;
+def : ReadAdvance<ReadFAdd16, 0>;
+def : ReadAdvance<ReadFAdd32, 0>;
+def : ReadAdvance<ReadFAdd64, 0>;
+def : ReadAdvance<ReadFMul16, 0>;
+def : ReadAdvance<ReadFMA16, 0>;
+def : ReadAdvance<ReadFMA16Addend, 0>;
+def : ReadAdvance<ReadFMul32, 0>;
+def : ReadAdvance<ReadFMA32, 0>;
+def : ReadAdvance<ReadFMA32Addend, 0>;
+def : ReadAdvance<ReadFMul64, 0>;
+def : ReadAdvance<ReadFMA64, 0>;
+def : ReadAdvance<ReadFMA64Addend, 0>;
+def : ReadAdvance<ReadFDiv16, 0>;
+def : ReadAdvance<ReadFDiv32, 0>;
+def : ReadAdvance<ReadFDiv64, 0>;
+def : ReadAdvance<ReadFSqrt16, 0>;
+def : ReadAdvance<ReadFSqrt32, 0>;
+def : ReadAdvance<ReadFSqrt64, 0>;
+def : ReadAdvance<ReadFCmp16, 0>;
+def : ReadAdvance<ReadFCmp32, 0>;
+def : ReadAdvance<ReadFCmp64, 0>;
+def : ReadAdvance<ReadFSGNJ16, 0>;
+def : ReadAdvance<ReadFSGNJ32, 0>;
+def : ReadAdvance<ReadFSGNJ64, 0>;
+def : ReadAdvance<ReadFMinMax16, 0>;
+def : ReadAdvance<ReadFMinMax32, 0>;
+def : ReadAdvance<ReadFMinMax64, 0>;
+def : ReadAdvance<ReadFCvtF16ToI32, 0>;
+def : ReadAdvance<ReadFCvtF16ToI64, 0>;
+def : ReadAdvance<ReadFCvtF32ToI32, 0>;
+def : ReadAdvance<ReadFCvtF32ToI64, 0>;
+def : ReadAdvance<ReadFCvtF64ToI32, 0>;
+def : ReadAdvance<ReadFCvtF64ToI64, 0>;
+def : ReadAdvance<ReadFCvtI32ToF16, 0>;
+def : ReadAdvance<ReadFCvtI32ToF32, 0>;
+def : ReadAdvance<ReadFCvtI32ToF64, 0>;
+def : ReadAdvance<ReadFCvtI64ToF16, 0>;
+def : ReadAdvance<ReadFCvtI64ToF32, 0>;
+def : ReadAdvance<ReadFCvtI64ToF64, 0>;
+def : ReadAdvance<ReadFCvtF32ToF64, 0>;
+def : ReadAdvance<ReadFCvtF64ToF32, 0>;
+def : ReadAdvance<ReadFCvtF16ToF32, 0>;
+def : ReadAdvance<ReadFCvtF32ToF16, 0>;
+def : ReadAdvance<ReadFCvtF16ToF64, 0>;
+def : ReadAdvance<ReadFCvtF64ToF16, 0>;
+def : ReadAdvance<ReadFMovF16ToI16, 0>;
+def : ReadAdvance<ReadFMovI16ToF16, 0>;
+def : ReadAdvance<ReadFMovF32ToI32, 0>;
+def : ReadAdvance<ReadFMovI32ToF32, 0>;
+def : ReadAdvance<ReadFMovF64ToI64, 0>;
+def : ReadAdvance<ReadFMovI64ToF64, 0>;
+def : ReadAdvance<ReadFClass16, 0>;
+def : ReadAdvance<ReadFClass32, 0>;
+def : ReadAdvance<ReadFClass64, 0>;
+
+// Bitmanip
+def : ReadAdvance<ReadRotateImm, 0>;
+def : ReadAdvance<ReadRotateImm32, 0>;
+def : ReadAdvance<ReadRotateReg, 0>;
+def : ReadAdvance<ReadRotateReg32, 0>;
+def : ReadAdvance<ReadCLZ, 0>;
+def : ReadAdvance<ReadCLZ32, 0>;
+def : ReadAdvance<ReadCTZ, 0>;
+def : ReadAdvance<ReadCTZ32, 0>;
+def : ReadAdvance<ReadCPOP, 0>;
+def : ReadAdvance<ReadCPOP32, 0>;
+def : ReadAdvance<ReadORCB, 0>;
+def : ReadAdvance<ReadIMinMax, 0>;
+def : ReadAdvance<ReadREV8, 0>;
+def : ReadAdvance<ReadSHXADD, 0>;
+def : ReadAdvance<ReadSHXADD32, 0>;
+
+//===----------------------------------------------------------------------===//
+// Unsupported extensions
+defm : UnsupportedSchedV;
+defm : UnsupportedSchedZabha;
+defm : UnsupportedSchedZbc;
+defm : UnsupportedSchedZbs;
+defm : UnsupportedSchedZbkb;
+defm : UnsupportedSchedZbkx;
+defm : UnsupportedSchedSFB;
+defm : UnsupportedSchedZfa;
+defm : UnsupportedSchedZvk;
+defm : UnsupportedSchedXsfvcp;
+}
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP500/alu.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP500/alu.s
new file mode 100644
index 00000000000000..d7791b73bf1bfd
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP500/alu.s
@@ -0,0 +1,200 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p550 -iterations=1 < %s | FileCheck %s
+
+add t0, t0, t0
+addw t2, t2, t2
+sub t1, t1, t1
+subw t3, t3, t3
+
+addi t0, t0, 100
+addiw t2, t2, 200
+
+and t2, t2, t2
+or t3, t3, t3
+xor t4, t4, t4
+
+andi t2, t2, 10
+ori t3, t3, 20
+xori t4, t4, 30
+
+sll t5, t5, t6
+srl t0, s0, t6
+sra s1, s1, t6
+
+slli t5, t5, 1
+srli t0, s0, 2
+srai s1, s1, 3
+
+mul s6, s6, s7
+mulw s4, s4, a2
+
+div a0, a0, a0
+divw a1, a1, a1
+rem a2, a2, a2
+remw a2, a2, a2
+
+rol t5, t5, t6
+ror t6, t6, t5
+rori t5, t5, 5
+
+rolw t5, t5, t6
+rorw t6, t6, t5
+roriw t5, t5, 5
+
+andn a0, a0, a1
+orn a1, a2, a3
+xnor a2, a3, a4
+
+min a3, a4, a5
+max a4, a5, a6
+minu a5, a6, a7
+maxu a6, a7, s0
+
+orc.b s0, s1
+rev8 s1, s2
+
+cpop t1, t1
+cpopw t2, t2
+
+sh1add t0, t1, t2
+sh2add t0, t1, t2
+sh3add t0, t1, t2
+
+add.uw s0, s1, s2
+sh1add.uw t0, t1, t2
+sh2add.uw t0, t1, t2
+sh3add.uw t0, t1, t2
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 48
+# CHECK-NEXT: Total Cycles: 120
+# CHECK-NEXT: Total uOps: 48
+
+# CHECK: Dispatch Width: 3
+# CHECK-NEXT: uOps Per Cycle: 0.40
+# CHECK-NEXT: IPC: 0.40
+# CHECK-NEXT: Block RThroughput: 106.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.33 add t0, t0, t0
+# CHECK-NEXT: 1 1 0.33 addw t2, t2, t2
+# CHECK-NEXT: 1 1 0.33 sub t1, t1, t1
+# CHECK-NEXT: 1 1 0.33 subw t3, t3, t3
+# CHECK-NEXT: 1 1 0.33 addi t0, t0, 100
+# CHECK-NEXT: 1 1 0.33 addiw t2, t2, 200
+# CHECK-NEXT: 1 1 0.33 and t2, t2, t2
+# CHECK-NEXT: 1 1 0.33 or t3, t3, t3
+# CHECK-NEXT: 1 1 0.33 xor t4, t4, t4
+# CHECK-NEXT: 1 1 0.33 andi t2, t2, 10
+# CHECK-NEXT: 1 1 0.33 ori t3, t3, 20
+# CHECK-NEXT: 1 1 0.33 xori t4, t4, 30
+# CHECK-NEXT: 1 1 0.33 sll t5, t5, t6
+# CHECK-NEXT: 1 1 0.33 srl t0, s0, t6
+# CHECK-NEXT: 1 1 0.33 sra s1, s1, t6
+# CHECK-NEXT: 1 1 0.33 slli t5, t5, 1
+# CHECK-NEXT: 1 1 0.33 srli t0, s0, 2
+# CHECK-NEXT: 1 1 0.33 srai s1, s1, 3
+# CHECK-NEXT: 1 3 1.00 mul s6, s6, s7
+# CHECK-NEXT: 1 3 1.00 mulw s4, s4, a2
+# CHECK-NEXT: 1 35 34.00 div a0, a0, a0
+# CHECK-NEXT: 1 20 19.00 divw a1, a1, a1
+# CHECK-NEXT: 1 35 34.00 rem a2, a2, a2
+# CHECK-NEXT: 1 20 19.00 remw a2, a2, a2
+# CHECK-NEXT: 1 1 0.33 rol t5, t5, t6
+# CHECK-NEXT: 1 1 0.33 ror t6, t6, t5
+# CHECK-NEXT: 1 1 0.33 rori t5, t5, 5
+# CHECK-NEXT: 1 1 0.33 rolw t5, t5, t6
+# CHECK-NEXT: 1 1 0.33 rorw t6, t6, t5
+# CHECK-NEXT: 1 1 0.33 roriw t5, t5, 5
+# CHECK-NEXT: 1 1 0.33 andn a0, a0, a1
+# CHECK-NEXT: 1 1 0.33 orn a1, a2, a3
+# CHECK-NEXT: 1 1 0.33 xnor a2, a3, a4
+# CHECK-NEXT: 1 1 0.33 min a3, a4, a5
+# CHECK-NEXT: 1 1 0.33 max a4, a5, a6
+# CHECK-NEXT: 1 1 0.33 minu a5, a6, a7
+# CHECK-NEXT: 1 1 0.33 maxu a6, a7, s0
+# CHECK-NEXT: 1 1 0.33 orc.b s0, s1
+# CHECK-NEXT: 1 1 0.33 rev8 s1, s2
+# CHECK-NEXT: 1 3 1.00 cpop t1, t1
+# CHECK-NEXT: 1 3 1.00 cpopw t2, t2
+# CHECK-NEXT: 1 1 0.33 sh1add t0, t1, t2
+# CHECK-NEXT: 1 1 0.33 sh2add t0, t1, t2
+# CHECK-NEXT: 1 1 0.33 sh3add t0, t1, t2
+# CHECK-NEXT: 1 1 0.33 add.uw s0, s1, s2
+# CHECK-NEXT: 1 1 0.33 sh1add.uw t0, t1, t2
+# CHECK-NEXT: 1 1 0.33 sh2add.uw t0, t1, t2
+# CHECK-NEXT: 1 1 0.33 sh3add.uw t0, t1, t2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP500Div
+# CHECK-NEXT: [1] - SiFiveP500FEXQ0
+# CHECK-NEXT: [2] - SiFiveP500FEXQ1
+# CHECK-NEXT: [3] - SiFiveP500FloatDiv
+# CHECK-NEXT: [4] - SiFiveP500IEXQ0
+# CHECK-NEXT: [5] - SiFiveP500IEXQ1
+# CHECK-NEXT: [6] - SiFiveP500IEXQ2
+# CHECK-NEXT: [7] - SiFiveP500Load
+# CHECK-NEXT: [8] - SiFiveP500Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8]
+# CHECK-NEXT: 106.00 - - - 14.00 15.00 19.00 - -
+
+# CHECK: Resource p...
[truncated]
|
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P550 falls between P450 and P650. It has 1 additional FEX pipe over P450. Mul and cpop latency are 3 instead of 2.
I've set the MicroOpBufferSize to 96 instead of 56 based on the ROB size measurement from https://chipsandcheese.com/p/inside-sifives-p550-microarchitecture I believe we set this value too low for P450 and P650 and should update them in a separate PR.