Skip to content

[AMDGPU][True16][MC] true16 for v_mad_u/i32_u/i16 #124781

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Jan 30, 2025
Merged

[AMDGPU][True16][MC] true16 for v_mad_u/i32_u/i16 #124781

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
8 changes: 4 additions & 4 deletions llvm/lib/Target/AMDGPU/VOP3Instructions.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -645,8 +645,8 @@ defm V_ADD_I16 : VOP3Inst_t16 <"v_add_i16", VOP_I16_I16_I16>;
defm V_SUB_I16 : VOP3Inst_t16 <"v_sub_i16", VOP_I16_I16_I16>;

let isCommutable = 1 in {
defm V_MAD_U32_U16 : VOP3Inst <"v_mad_u32_u16", VOP3_Profile<VOP_I32_I16_I16_I32, VOP3_OPSEL>>;
defm V_MAD_I32_I16 : VOP3Inst <"v_mad_i32_i16", VOP3_Profile<VOP_I32_I16_I16_I32, VOP3_OPSEL>>;
defm V_MAD_U32_U16 : VOP3Inst_t16 <"v_mad_u32_u16", VOP_I32_I16_I16_I32>;
defm V_MAD_I32_I16 : VOP3Inst_t16 <"v_mad_i32_i16", VOP_I32_I16_I16_I32>;
} // End isCommutable = 1

defm V_CVT_PKNORM_I16_F16 : VOP3Inst_t16 <"v_cvt_pknorm_i16_f16", VOP_B32_F16_F16>;
Expand Down Expand Up @@ -1736,8 +1736,8 @@ defm V_ADD3_U32 : VOP3_Realtriple_gfx11_gfx12<0x255>;
defm V_LSHL_OR_B32 : VOP3_Realtriple_gfx11_gfx12<0x256>;
defm V_AND_OR_B32 : VOP3_Realtriple_gfx11_gfx12<0x257>;
defm V_OR3_B32 : VOP3_Realtriple_gfx11_gfx12<0x258>;
defm V_MAD_U32_U16 : VOP3_Realtriple_gfx11_gfx12<0x259>;
defm V_MAD_I32_I16 : VOP3_Realtriple_gfx11_gfx12<0x25a>;
defm V_MAD_U32_U16 : VOP3_Realtriple_t16_and_fake16_gfx11_gfx12<0x259, "v_mad_u32_u16">;
defm V_MAD_I32_I16 : VOP3_Realtriple_t16_and_fake16_gfx11_gfx12<0x25a, "v_mad_i32_i16">;
defm V_PERMLANE16_B32 : VOP3_Real_Base_gfx11_gfx12<0x25b>;
defm V_PERMLANEX16_B32 : VOP3_Real_Base_gfx11_gfx12<0x25c>;
defm V_MAXMIN_F32 : VOP3_Realtriple_gfx11<0x25e>;
Expand Down
40 changes: 32 additions & 8 deletions llvm/test/MC/AMDGPU/gfx11_asm_vop3.s
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2906,11 +2906,11 @@ v_mad_i16 v5.l, -1, exec_hi, src_scc
v_mad_i16 v5.l, src_scc, vcc_lo, -1
// GFX11: v_mad_i16 v5.l, src_scc, vcc_lo, -1 ; encoding: [0x05,0x00,0x53,0xd6,0xfd,0xd4,0x04,0x03]

v_mad_i32_i16 v5, v1, v2, v3
// GFX11: v_mad_i32_i16 v5, v1, v2, v3 ; encoding: [0x05,0x00,0x5a,0xd6,0x01,0x05,0x0e,0x04]
v_mad_i32_i16 v5, v1.l, v2.l, v3
// GFX11: v_mad_i32_i16 v5, v1.l, v2.l, v3 ; encoding: [0x05,0x00,0x5a,0xd6,0x01,0x05,0x0e,0x04]

v_mad_i32_i16 v5, v255, v255, s3
// GFX11: v_mad_i32_i16 v5, v255, v255, s3 ; encoding: [0x05,0x00,0x5a,0xd6,0xff,0xff,0x0f,0x00]
v_mad_i32_i16 v5, v255.l, v255.l, s3
// GFX11: v_mad_i32_i16 v5, v255.l, v255.l, s3 ; encoding: [0x05,0x00,0x5a,0xd6,0xff,0xff,0x0f,0x00]

v_mad_i32_i16 v5, s1, s2, v255
// GFX11: v_mad_i32_i16 v5, s1, s2, v255 ; encoding: [0x05,0x00,0x5a,0xd6,0x01,0x04,0xfc,0x07]
Expand Down Expand Up @@ -2951,6 +2951,18 @@ v_mad_i32_i16 v5, src_scc, vcc_lo, src_scc op_sel:[1,0,0,0]
v_mad_i32_i16 v255, 0xfe0b, vcc_hi, 0.5 op_sel:[0,1,0,0] clamp
// GFX11: v_mad_i32_i16 v255, 0xfe0b, vcc_hi, 0.5 op_sel:[0,1,0,0] clamp ; encoding: [0xff,0x90,0x5a,0xd6,0xff,0xd6,0xc0,0x03,0x0b,0xfe,0x00,0x00]

v_mad_i32_i16 v5, v1.h, v2.l, v3
// GFX11: v_mad_i32_i16 v5, v1.h, v2.l, v3 op_sel:[1,0,0,0] ; encoding: [0x05,0x08,0x5a,0xd6,0x01,0x05,0x0e,0x04]

v_mad_i32_i16 v5, v255.l, v255.h, s3
// GFX11: v_mad_i32_i16 v5, v255.l, v255.h, s3 op_sel:[0,1,0,0] ; encoding: [0x05,0x10,0x5a,0xd6,0xff,0xff,0x0f,0x00]

v_mad_i32_i16 v5, src_scc, vcc_lo, src_scc
// GFX11: v_mad_i32_i16 v5, src_scc, vcc_lo, src_scc ; encoding: [0x05,0x00,0x5a,0xd6,0xfd,0xd4,0xf4,0x03]

v_mad_i32_i16 v255, 0xfe0b, vcc_hi, 0.5 clamp
// GFX11: v_mad_i32_i16 v255, 0xfe0b, vcc_hi, 0.5 clamp ; encoding: [0xff,0x80,0x5a,0xd6,0xff,0xd6,0xc0,0x03,0x0b,0xfe,0x00,0x00]

v_mad_i32_i24 v5, v1, v2, s3
// GFX11: v_mad_i32_i24 v5, v1, v2, s3 ; encoding: [0x05,0x00,0x0a,0xd6,0x01,0x05,0x0e,0x00]

Expand Down Expand Up @@ -3134,11 +3146,11 @@ v_mad_u16 v5.l, -1, exec_hi, src_scc
v_mad_u16 v5.l, src_scc, vcc_lo, -1
// GFX11: v_mad_u16 v5.l, src_scc, vcc_lo, -1 ; encoding: [0x05,0x00,0x41,0xd6,0xfd,0xd4,0x04,0x03]

v_mad_u32_u16 v5, v1, v2, v3
// GFX11: v_mad_u32_u16 v5, v1, v2, v3 ; encoding: [0x05,0x00,0x59,0xd6,0x01,0x05,0x0e,0x04]
v_mad_u32_u16 v5, v1.l, v2.l, v3
// GFX11: v_mad_u32_u16 v5, v1.l, v2.l, v3 ; encoding: [0x05,0x00,0x59,0xd6,0x01,0x05,0x0e,0x04]

v_mad_u32_u16 v5, v255, v255, s3
// GFX11: v_mad_u32_u16 v5, v255, v255, s3 ; encoding: [0x05,0x00,0x59,0xd6,0xff,0xff,0x0f,0x00]
v_mad_u32_u16 v5, v255.l, v255.l, s3
// GFX11: v_mad_u32_u16 v5, v255.l, v255.l, s3 ; encoding: [0x05,0x00,0x59,0xd6,0xff,0xff,0x0f,0x00]

v_mad_u32_u16 v5, s1, s2, v255
// GFX11: v_mad_u32_u16 v5, s1, s2, v255 ; encoding: [0x05,0x00,0x59,0xd6,0x01,0x04,0xfc,0x07]
Expand Down Expand Up @@ -3179,6 +3191,18 @@ v_mad_u32_u16 v5, src_scc, vcc_lo, src_scc op_sel:[1,0,0,0]
v_mad_u32_u16 v255, 0xfe0b, vcc_hi, 0.5 op_sel:[0,1,0,0] clamp
// GFX11: v_mad_u32_u16 v255, 0xfe0b, vcc_hi, 0.5 op_sel:[0,1,0,0] clamp ; encoding: [0xff,0x90,0x59,0xd6,0xff,0xd6,0xc0,0x03,0x0b,0xfe,0x00,0x00]

v_mad_u32_u16 v5, v1.h, v2.l, v3
// GFX11: v_mad_u32_u16 v5, v1.h, v2.l, v3 op_sel:[1,0,0,0] ; encoding: [0x05,0x08,0x59,0xd6,0x01,0x05,0x0e,0x04]

v_mad_u32_u16 v5, v255.l, v255.h, s3
// GFX11: v_mad_u32_u16 v5, v255.l, v255.h, s3 op_sel:[0,1,0,0] ; encoding: [0x05,0x10,0x59,0xd6,0xff,0xff,0x0f,0x00]

v_mad_u32_u16 v5, src_scc, vcc_lo, src_scc
// GFX11: v_mad_u32_u16 v5, src_scc, vcc_lo, src_scc ; encoding: [0x05,0x00,0x59,0xd6,0xfd,0xd4,0xf4,0x03]

v_mad_u32_u16 v255, 0xfe0b, vcc_hi, 0.5 clamp
// GFX11: v_mad_u32_u16 v255, 0xfe0b, vcc_hi, 0.5 clamp ; encoding: [0xff,0x80,0x59,0xd6,0xff,0xd6,0xc0,0x03,0x0b,0xfe,0x00,0x00]

v_mad_u32_u24 v5, v1, v2, s3
// GFX11: v_mad_u32_u24 v5, v1, v2, s3 ; encoding: [0x05,0x00,0x0b,0xd6,0x01,0x05,0x0e,0x00]

Expand Down
Loading