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koachan
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@koachan koachan commented Jan 31, 2025

Add IAS flag handling for ISA levels we support in LLVM.

Created using spr 1.3.4
@llvmbot llvmbot added clang Clang issues not falling into any other category clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' labels Jan 31, 2025
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llvmbot commented Jan 31, 2025

@llvm/pr-subscribers-clang-driver

@llvm/pr-subscribers-clang

Author: Koakuma (koachan)

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Add IAS flag handling for ISA levels we support in LLVM.


Full diff: https://github.com/llvm/llvm-project/pull/125151.diff

2 Files Affected:

  • (modified) clang/lib/Driver/ToolChains/Clang.cpp (+32)
  • (added) clang/test/Driver/sparc-ias-Wa.s (+60)
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp
index 518113e20cb063..832766e2f8487a 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -2593,6 +2593,7 @@ static void CollectArgsForIntegratedAssembler(Compilation &C,
   bool UseNoExecStack = false;
   bool Msa = false;
   const char *MipsTargetFeature = nullptr;
+  llvm::SmallVector<const char *> SparcTargetFeatures;
   StringRef ImplicitIt;
   for (const Arg *A :
        Args.filtered(options::OPT_Wa_COMMA, options::OPT_Xassembler,
@@ -2738,6 +2739,31 @@ static void CollectArgsForIntegratedAssembler(Compilation &C,
         if (MipsTargetFeature)
           continue;
         break;
+
+      case llvm::Triple::sparc:
+      case llvm::Triple::sparcel:
+      case llvm::Triple::sparcv9:
+        if (Value == "--undeclared-regs") {
+          // LLVM already allows undeclared use of G registers, so this option
+          // becomes a no-op. This solely exists for GNU compatibility.
+          // TODO implement --no-undeclared-regs
+          continue;
+        }
+        SparcTargetFeatures =
+            llvm::StringSwitch<llvm::SmallVector<const char *>>(Value)
+                .Case("-Av8", {"-v8plus"})
+                .Case("-Av8plus", {"+v8plus", "+v9"})
+                .Case("-Av8plusa", {"+v8plus", "+v9", "+vis"})
+                .Case("-Av8plusb", {"+v8plus", "+v9", "+vis", "+vis2"})
+                .Case("-Av8plusd", {"+v8plus", "+v9", "+vis", "+vis2", "+vis3"})
+                .Case("-Av9", {"+v9"})
+                .Case("-Av9a", {"+v9", "+vis"})
+                .Case("-Av9b", {"+v9", "+vis", "+vis2"})
+                .Case("-Av9d", {"+v9", "+vis", "+vis2", "+vis3"})
+                .Default({});
+        if (!SparcTargetFeatures.empty())
+          continue;
+        break;
       }
 
       if (Value == "-force_cpusubtype_ALL") {
@@ -2842,6 +2868,12 @@ static void CollectArgsForIntegratedAssembler(Compilation &C,
     CmdArgs.push_back("-target-feature");
     CmdArgs.push_back(MipsTargetFeature);
   }
+  if (!SparcTargetFeatures.empty()) {
+    for (const char *Feature : SparcTargetFeatures) {
+      CmdArgs.push_back("-target-feature");
+      CmdArgs.push_back(Feature);
+    }
+  }
 
   // forward -fembed-bitcode to assmebler
   if (C.getDriver().embedBitcodeEnabled() ||
diff --git a/clang/test/Driver/sparc-ias-Wa.s b/clang/test/Driver/sparc-ias-Wa.s
new file mode 100644
index 00000000000000..79456c02935be1
--- /dev/null
+++ b/clang/test/Driver/sparc-ias-Wa.s
@@ -0,0 +1,60 @@
+// RUN: %clang --target=sparc-linux-gnu -### -fintegrated-as -c %s -Wa,-Av8 2>&1 | \
+// RUN:   FileCheck -check-prefix=V8 %s
+// V8: -cc1as
+// V8: "-target-feature" "-v8plus"
+
+// RUN: %clang --target=sparc-linux-gnu -### -fintegrated-as -c %s -Wa,-Av8plus 2>&1 | \
+// RUN:   FileCheck -check-prefix=V8PLUS %s
+// V8PLUS: -cc1as
+// V8PLUS: "-target-feature" "+v8plus"
+// V8PLUS: "-target-feature" "+v9"
+
+// RUN: %clang --target=sparc-linux-gnu -### -fintegrated-as -c %s -Wa,-Av8plusa 2>&1 | \
+// RUN:   FileCheck -check-prefix=V8PLUSA %s
+// V8PLUSA: -cc1as
+// V8PLUSA: "-target-feature" "+v8plus"
+// V8PLUSA: "-target-feature" "+v9"
+// V8PLUSA: "-target-feature" "+vis"
+
+// RUN: %clang --target=sparc-linux-gnu -### -fintegrated-as -c %s -Wa,-Av8plusb 2>&1 | \
+// RUN:   FileCheck -check-prefix=V8PLUSB %s
+// V8PLUSB: -cc1as
+// V8PLUSB: "-target-feature" "+v8plus"
+// V8PLUSB: "-target-feature" "+v9"
+// V8PLUSB: "-target-feature" "+vis"
+// V8PLUSB: "-target-feature" "+vis2"
+
+// RUN: %clang --target=sparc-linux-gnu -### -fintegrated-as -c %s -Wa,-Av8plusd 2>&1 | \
+// RUN:   FileCheck -check-prefix=V8PLUSD %s
+// V8PLUSD: -cc1as
+// V8PLUSD: "-target-feature" "+v8plus"
+// V8PLUSD: "-target-feature" "+v9"
+// V8PLUSD: "-target-feature" "+vis"
+// V8PLUSD: "-target-feature" "+vis2"
+// V8PLUSD: "-target-feature" "+vis3"
+
+// RUN: %clang --target=sparc-linux-gnu -### -fintegrated-as -c %s -Wa,-Av9 2>&1 | \
+// RUN:   FileCheck -check-prefix=V9 %s
+// V9: -cc1as
+// V9: "-target-feature" "+v9"
+
+// RUN: %clang --target=sparc-linux-gnu -### -fintegrated-as -c %s -Wa,-Av9a 2>&1 | \
+// RUN:   FileCheck -check-prefix=V9A %s
+// V9A: -cc1as
+// V9A: "-target-feature" "+v9"
+// V9A: "-target-feature" "+vis"
+
+// RUN: %clang --target=sparc-linux-gnu -### -fintegrated-as -c %s -Wa,-Av9b 2>&1 | \
+// RUN:   FileCheck -check-prefix=V9B %s
+// V9B: -cc1as
+// V9B: "-target-feature" "+v9"
+// V9B: "-target-feature" "+vis"
+// V9B: "-target-feature" "+vis2"
+
+// RUN: %clang --target=sparc-linux-gnu -### -fintegrated-as -c %s -Wa,-Av9d 2>&1 | \
+// RUN:   FileCheck -check-prefix=V9D %s
+// V9D: -cc1as
+// V9D: "-target-feature" "+v9"
+// V9D: "-target-feature" "+vis"
+// V9D: "-target-feature" "+vis2"
+// V9D: "-target-feature" "+vis3"

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brad0 commented Feb 2, 2025

@MaskRay

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brad0 commented Feb 7, 2025

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We try to support very few -Wa,... options for the integrated assembler, since as you can see, the number of lines increases quite a lot. if this option is so frequently used, i think this is ok.

Created using spr 1.3.5

[skip ci]
Created using spr 1.3.5
@koachan koachan changed the base branch from users/koachan/spr/main.sparcias-add-ias-flag-handling-for-isa-levels to main February 13, 2025 03:22
@koachan koachan merged commit 30a9941 into main Feb 13, 2025
10 of 11 checks passed
@koachan koachan deleted the users/koachan/spr/sparcias-add-ias-flag-handling-for-isa-levels branch February 13, 2025 03:22
github-actions bot pushed a commit to arm/arm-toolchain that referenced this pull request Feb 13, 2025
Add IAS flag handling for ISA levels we support in LLVM.

Reviewers: MaskRay, rorth, brad0, s-barannikov

Reviewed By: MaskRay

Pull Request: llvm/llvm-project#125151
flovent pushed a commit to flovent/llvm-project that referenced this pull request Feb 13, 2025
Add IAS flag handling for ISA levels we support in LLVM.

Reviewers: MaskRay, rorth, brad0, s-barannikov

Reviewed By: MaskRay

Pull Request: llvm#125151
joaosaffran pushed a commit to joaosaffran/llvm-project that referenced this pull request Feb 14, 2025
Add IAS flag handling for ISA levels we support in LLVM.

Reviewers: MaskRay, rorth, brad0, s-barannikov

Reviewed By: MaskRay

Pull Request: llvm#125151
sivan-shani pushed a commit to sivan-shani/llvm-project that referenced this pull request Feb 24, 2025
Add IAS flag handling for ISA levels we support in LLVM.

Reviewers: MaskRay, rorth, brad0, s-barannikov

Reviewed By: MaskRay

Pull Request: llvm#125151
bob-beck pushed a commit to openbsd/ports that referenced this pull request Mar 10, 2025
SPARC architecture and for setting the default to vis/-Av9a.
Needed for building base and xenocara on sparc64.
llvm/llvm-project#125151
llvm/llvm-project#130108
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