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[RISCV] Simplify usage of SplatPat_simm5_plus1. NFC #125340

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Merged
merged 2 commits into from
Feb 1, 2025
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[RISCV] Simplify usage of SplatPat_simm5_plus1. NFC #125340

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ed4c019
[RISCV] Simplify usage of SplatPat_simm5_plus1. NFC
topperc Feb 1, 2025
69bcf1d
fixup! clang-format
topperc Feb 1, 2025
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15 changes: 11 additions & 4 deletions llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3538,7 +3538,8 @@ bool RISCVDAGToDAGISel::selectVSplat(SDValue N, SDValue &SplatVal) {
static bool selectVSplatImmHelper(SDValue N, SDValue &SplatVal,
SelectionDAG &DAG,
const RISCVSubtarget &Subtarget,
std::function<bool(int64_t)> ValidateImm) {
std::function<bool(int64_t)> ValidateImm,
bool Decrement = false) {
SDValue Splat = findVSplat(N);
if (!Splat || !isa<ConstantSDNode>(Splat.getOperand(1)))
return false;
Expand All @@ -3561,6 +3562,9 @@ static bool selectVSplatImmHelper(SDValue N, SDValue &SplatVal,
if (!ValidateImm(SplatImm))
return false;

if (Decrement)
SplatImm -= 1;

SplatVal =
DAG.getSignedTargetConstant(SplatImm, SDLoc(N), Subtarget.getXLenVT());
return true;
Expand All @@ -3574,15 +3578,18 @@ bool RISCVDAGToDAGISel::selectVSplatSimm5(SDValue N, SDValue &SplatVal) {
bool RISCVDAGToDAGISel::selectVSplatSimm5Plus1(SDValue N, SDValue &SplatVal) {
return selectVSplatImmHelper(
N, SplatVal, *CurDAG, *Subtarget,
[](int64_t Imm) { return (isInt<5>(Imm) && Imm != -16) || Imm == 16; });
[](int64_t Imm) { return (isInt<5>(Imm) && Imm != -16) || Imm == 16; },
/*Decrement=*/true);
}

bool RISCVDAGToDAGISel::selectVSplatSimm5Plus1NonZero(SDValue N,
SDValue &SplatVal) {
return selectVSplatImmHelper(
N, SplatVal, *CurDAG, *Subtarget, [](int64_t Imm) {
N, SplatVal, *CurDAG, *Subtarget,
[](int64_t Imm) {
return Imm != 0 && ((isInt<5>(Imm) && Imm != -16) || Imm == 16);
});
},
/*Decrement=*/true);
}

bool RISCVDAGToDAGISel::selectVSplatUimm(SDValue N, unsigned Bits,
Expand Down
41 changes: 11 additions & 30 deletions llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
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Expand Up @@ -313,29 +313,10 @@ multiclass VPatIntegerSetCCSDNode_VX_Swappable<string instruction_name,
SplatPat, GPR>;

multiclass VPatIntegerSetCCSDNode_VI_Swappable<string instruction_name,
CondCode cc, CondCode invcc>
CondCode cc, CondCode invcc,
ComplexPattern splatpat_kind = SplatPat_simm5>
: VPatIntegerSetCCSDNode_XI_Swappable<instruction_name, cc, invcc, "VI",
SplatPat_simm5, simm5>;

multiclass VPatIntegerSetCCSDNode_VIPlus1_Swappable<string instruction_name,
CondCode cc, CondCode invcc,
ComplexPattern splatpat_kind> {
foreach vti = AllIntegerVectors in {
defvar instruction = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX);
let Predicates = GetVTypePredicates<vti>.Predicates in {
def : Pat<(vti.Mask (setcc (vti.Vector vti.RegClass:$rs1),
(vti.Vector (splatpat_kind simm5:$rs2)),
cc)),
(instruction vti.RegClass:$rs1, (DecImm simm5:$rs2),
vti.AVL, vti.Log2SEW)>;
def : Pat<(vti.Mask (setcc (vti.Vector (splatpat_kind simm5:$rs2)),
(vti.Vector vti.RegClass:$rs1),
invcc)),
(instruction vti.RegClass:$rs1, (DecImm simm5:$rs2),
vti.AVL, vti.Log2SEW)>;
}
}
}
splatpat_kind, simm5>;

multiclass VPatFPSetCCSDNode_VV_VF_FV<CondCode cc,
string inst_name,
Expand Down Expand Up @@ -1021,14 +1002,14 @@ defm : VPatIntegerSetCCSDNode_VI_Swappable<"PseudoVMSLEU", SETULE, SETUGE>;
defm : VPatIntegerSetCCSDNode_VI_Swappable<"PseudoVMSGT", SETGT, SETLT>;
defm : VPatIntegerSetCCSDNode_VI_Swappable<"PseudoVMSGTU", SETUGT, SETULT>;

defm : VPatIntegerSetCCSDNode_VIPlus1_Swappable<"PseudoVMSLE", SETLT, SETGT,
SplatPat_simm5_plus1>;
defm : VPatIntegerSetCCSDNode_VIPlus1_Swappable<"PseudoVMSLEU", SETULT, SETUGT,
SplatPat_simm5_plus1_nonzero>;
defm : VPatIntegerSetCCSDNode_VIPlus1_Swappable<"PseudoVMSGT", SETGE, SETLE,
SplatPat_simm5_plus1>;
defm : VPatIntegerSetCCSDNode_VIPlus1_Swappable<"PseudoVMSGTU", SETUGE, SETULE,
SplatPat_simm5_plus1_nonzero>;
defm : VPatIntegerSetCCSDNode_VI_Swappable<"PseudoVMSLE", SETLT, SETGT,
SplatPat_simm5_plus1>;
defm : VPatIntegerSetCCSDNode_VI_Swappable<"PseudoVMSLEU", SETULT, SETUGT,
SplatPat_simm5_plus1_nonzero>;
defm : VPatIntegerSetCCSDNode_VI_Swappable<"PseudoVMSGT", SETGE, SETLE,
SplatPat_simm5_plus1>;
defm : VPatIntegerSetCCSDNode_VI_Swappable<"PseudoVMSGTU", SETUGE, SETULE,
SplatPat_simm5_plus1_nonzero>;

// 11.9. Vector Integer Min/Max Instructions
defm : VPatBinarySDNode_VV_VX<umin, "PseudoVMINU">;
Expand Down
48 changes: 12 additions & 36 deletions llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1052,40 +1052,16 @@ multiclass VPatIntegerSetCCVL_VX_Swappable<VTypeInfo vti, string instruction_nam
}

multiclass VPatIntegerSetCCVL_VI_Swappable<VTypeInfo vti, string instruction_name,
CondCode cc, CondCode invcc> {
defvar instruction_masked = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX#"_MASK");
def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1),
(SplatPat_simm5 simm5:$rs2), cc,
VR:$passthru,
(vti.Mask V0),
VLOpFrag)),
(instruction_masked VR:$passthru, vti.RegClass:$rs1,
XLenVT:$rs2, (vti.Mask V0), GPR:$vl,
vti.Log2SEW)>;

// FIXME: Can do some canonicalization to remove these patterns.
def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat_simm5 simm5:$rs2),
(vti.Vector vti.RegClass:$rs1), invcc,
VR:$passthru,
(vti.Mask V0),
VLOpFrag)),
(instruction_masked VR:$passthru, vti.RegClass:$rs1,
simm5:$rs2, (vti.Mask V0), GPR:$vl,
vti.Log2SEW)>;
}

multiclass VPatIntegerSetCCVL_VIPlus1_Swappable<VTypeInfo vti,
string instruction_name,
CondCode cc, CondCode invcc,
ComplexPattern splatpat_kind> {
CondCode cc, CondCode invcc,
ComplexPattern splatpat_kind = SplatPat_simm5> {
defvar instruction_masked = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX#"_MASK");
def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1),
(splatpat_kind simm5:$rs2), cc,
VR:$passthru,
(vti.Mask V0),
VLOpFrag)),
(instruction_masked VR:$passthru, vti.RegClass:$rs1,
(DecImm simm5:$rs2), (vti.Mask V0), GPR:$vl,
XLenVT:$rs2, (vti.Mask V0), GPR:$vl,
vti.Log2SEW)>;

// FIXME: Can do some canonicalization to remove these patterns.
Expand All @@ -1095,7 +1071,7 @@ multiclass VPatIntegerSetCCVL_VIPlus1_Swappable<VTypeInfo vti,
(vti.Mask V0),
VLOpFrag)),
(instruction_masked VR:$passthru, vti.RegClass:$rs1,
(DecImm simm5:$rs2), (vti.Mask V0), GPR:$vl,
simm5:$rs2, (vti.Mask V0), GPR:$vl,
vti.Log2SEW)>;
}

Expand Down Expand Up @@ -2173,14 +2149,14 @@ foreach vti = AllIntegerVectors in {
defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSGT", SETGT, SETLT>;
defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSGTU", SETUGT, SETULT>;

defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSLE", SETLT, SETGT,
SplatPat_simm5_plus1>;
defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSLEU", SETULT, SETUGT,
SplatPat_simm5_plus1_nonzero>;
defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSGT", SETGE, SETLE,
SplatPat_simm5_plus1>;
defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSGTU", SETUGE, SETULE,
SplatPat_simm5_plus1_nonzero>;
defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSLE", SETLT, SETGT,
SplatPat_simm5_plus1>;
defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSLEU", SETULT, SETUGT,
SplatPat_simm5_plus1_nonzero>;
defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSGT", SETGE, SETLE,
SplatPat_simm5_plus1>;
defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSGTU", SETUGE, SETULE,
SplatPat_simm5_plus1_nonzero>;
}
} // foreach vti = AllIntegerVectors

Expand Down