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[AMDGPU][True16][MC] Generate op_sel operands for VOPC instructions #125561

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20 changes: 16 additions & 4 deletions llvm/lib/Target/AMDGPU/VOPCInstructions.td
Original file line number Diff line number Diff line change
Expand Up @@ -389,10 +389,10 @@ multiclass VOPC_Pseudos <string opName,
let SchedRW = P.Schedule;
let isCompare = 1;
let isCommutable = 1;
let AsmMatchConverter =
!if (P.HasOpSel, "cvtVOP3OpSel",
!if (!or(P.HasModifiers, P.HasOMod, P.HasIntClamp), "cvtVOP3",
""));
let AsmMatchConverter = !cond(
P.HasOpSel : "cvtVOP3OpSel",
!or(P.HasModifiers, P.HasOMod, P.HasIntClamp) : "cvtVOP3",
1 : "");
}

if P.HasExtSDWA then
Expand Down Expand Up @@ -454,6 +454,10 @@ multiclass VOPCX_Pseudos <string opName,
let isCommutable = 1;
let SubtargetPredicate = HasNoSdstCMPX;
let IsVCMPX = 1;
let AsmMatchConverter = !cond(
P_NoSDst.HasOpSel : "cvtVOP3OpSel",
!or(P_NoSDst.HasModifiers, P_NoSDst.HasOMod, P_NoSDst.HasIntClamp) : "cvtVOP3",
1 : "");
}

if P_NoSDst.HasExtSDWA then
Expand Down Expand Up @@ -1079,6 +1083,10 @@ multiclass VOPC_Class_Pseudos <string opName, VOPC_Profile p, bit DefExec,
VCMPXNoSDstTable<1, opName#"_e64"> {
let Defs = !if(DefExec, [EXEC], []);
let SchedRW = p.Schedule;
let AsmMatchConverter = !cond(
p.HasOpSel : "cvtVOP3OpSel",
!or(p.HasModifiers, p.HasOMod, p.HasIntClamp) : "cvtVOP3",
1 : "");
}

if p.HasExtSDWA then
Expand Down Expand Up @@ -1127,6 +1135,10 @@ multiclass VOPCX_Class_Pseudos <string opName,
let Defs = [EXEC];
let SchedRW = P_NoSDst.Schedule;
let SubtargetPredicate = HasNoSdstCMPX;
let AsmMatchConverter = !cond(
P_NoSDst.HasOpSel : "cvtVOP3OpSel",
!or(P_NoSDst.HasModifiers, P_NoSDst.HasOMod, P_NoSDst.HasIntClamp) : "cvtVOP3",
1 : "");
}

if P_NoSDst.HasExtSDWA then
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopc.s
Original file line number Diff line number Diff line change
Expand Up @@ -128,19 +128,19 @@ v_cmp_class_f16_e64 vcc_lo, 0.5, m0
// W64-ERR: :[[@LINE-2]]:21: error: invalid operand for instruction

v_cmp_class_f16_e64 s5, v255.h, v2.l
// W32: v_cmp_class_f16_e64 s5, v255.h, v2.l ; encoding: [0x05,0x08,0x7d,0xd4,0xff,0x05,0x02,0x00]
// W32: v_cmp_class_f16_e64 s5, v255.h, v2.l op_sel:[1,0,0] ; encoding: [0x05,0x08,0x7d,0xd4,0xff,0x05,0x02,0x00]
// W64-ERR: :[[@LINE-2]]:21: error: invalid operand for instruction

v_cmp_class_f16_e64 s5, s105, v255.h
// W32: v_cmp_class_f16_e64 s5, s105, v255.h ; encoding: [0x05,0x10,0x7d,0xd4,0x69,0xfe,0x03,0x00]
// W32: v_cmp_class_f16_e64 s5, s105, v255.h op_sel:[0,1,0] ; encoding: [0x05,0x10,0x7d,0xd4,0x69,0xfe,0x03,0x00]
// W64-ERR: :[[@LINE-2]]:21: error: invalid operand for instruction

v_cmp_class_f16_e64 s[10:11], v255.h, v2.l
// W64: v_cmp_class_f16_e64 s[10:11], v255.h, v2.l ; encoding: [0x0a,0x08,0x7d,0xd4,0xff,0x05,0x02,0x00]
// W64: v_cmp_class_f16_e64 s[10:11], v255.h, v2.l op_sel:[1,0,0] ; encoding: [0x0a,0x08,0x7d,0xd4,0xff,0x05,0x02,0x00]
// W32-ERR: :[[@LINE-2]]:21: error: invalid operand for instruction

v_cmp_class_f16_e64 s[10:11], s105, v255.h
// W64: v_cmp_class_f16_e64 s[10:11], s105, v255.h ; encoding: [0x0a,0x10,0x7d,0xd4,0x69,0xfe,0x03,0x00]
// W64: v_cmp_class_f16_e64 s[10:11], s105, v255.h op_sel:[0,1,0] ; encoding: [0x0a,0x10,0x7d,0xd4,0x69,0xfe,0x03,0x00]
// W32-ERR: :[[@LINE-2]]:21: error: invalid operand for instruction

v_cmp_class_f32_e64 s5, v1, v2
Expand Down
118 changes: 59 additions & 59 deletions llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopcx.s

Large diffs are not rendered by default.

18 changes: 9 additions & 9 deletions llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_promote.s
Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 %s

v_cmp_class_f16 vcc, v1.h, v255.h
// GFX11: v_cmp_class_f16_e64 vcc, v1.h, v255.h ; encoding: [0x6a,0x18,0x7d,0xd4,0x01,0xff,0x03,0x00]
// GFX11: v_cmp_class_f16_e64 vcc, v1.h, v255.h op_sel:[1,1,0] ; encoding: [0x6a,0x18,0x7d,0xd4,0x01,0xff,0x03,0x00]

v_cmp_class_f16 vcc, v1.h, v255.h dpp8:[7,6,5,4,3,2,1,0]
// GFX11: v_cmp_class_f16_e64_dpp vcc, v1.h, v255.h op_sel:[1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x18,0x7d,0xd4,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05]
Expand All @@ -20,10 +20,10 @@ v_cmp_class_f16 vcc, v1.l, v255.l quad_perm:[3,2,1,0]
// GFX11: v_cmp_class_f16_e64_dpp vcc, v1.l, v255.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x7d,0xd4,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff]

v_cmp_class_f16 vcc, v127.h, v255.h
// GFX11: v_cmp_class_f16_e64 vcc, v127.h, v255.h ; encoding: [0x6a,0x18,0x7d,0xd4,0x7f,0xff,0x03,0x00]
// GFX11: v_cmp_class_f16_e64 vcc, v127.h, v255.h op_sel:[1,1,0] ; encoding: [0x6a,0x18,0x7d,0xd4,0x7f,0xff,0x03,0x00]

v_cmp_class_f16 vcc, v127.h, v255.h
// GFX11: v_cmp_class_f16_e64 vcc, v127.h, v255.h ; encoding: [0x6a,0x18,0x7d,0xd4,0x7f,0xff,0x03,0x00]
// GFX11: v_cmp_class_f16_e64 vcc, v127.h, v255.h op_sel:[1,1,0] ; encoding: [0x6a,0x18,0x7d,0xd4,0x7f,0xff,0x03,0x00]

v_cmp_class_f16 vcc, v127.h, v255.h dpp8:[7,6,5,4,3,2,1,0]
// GFX11: v_cmp_class_f16_e64_dpp vcc, v127.h, v255.h op_sel:[1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x18,0x7d,0xd4,0xe9,0xfe,0x03,0x00,0x7f,0x77,0x39,0x05]
Expand Down Expand Up @@ -56,10 +56,10 @@ v_cmp_class_f16 vcc, v127.l, v255.l quad_perm:[3,2,1,0]
// GFX11: v_cmp_class_f16_e64_dpp vcc, v127.l, v255.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x7d,0xd4,0xfa,0xfe,0x03,0x00,0x7f,0x1b,0x00,0xff]

v_cmp_class_f16 vcc, v128.h, v2.h
// GFX11: v_cmp_class_f16_e64 vcc, v128.h, v2.h ; encoding: [0x6a,0x18,0x7d,0xd4,0x80,0x05,0x02,0x00]
// GFX11: v_cmp_class_f16_e64 vcc, v128.h, v2.h op_sel:[1,1,0] ; encoding: [0x6a,0x18,0x7d,0xd4,0x80,0x05,0x02,0x00]

v_cmp_class_f16 vcc, v128.h, v2.h
// GFX11: v_cmp_class_f16_e64 vcc, v128.h, v2.h ; encoding: [0x6a,0x18,0x7d,0xd4,0x80,0x05,0x02,0x00]
// GFX11: v_cmp_class_f16_e64 vcc, v128.h, v2.h op_sel:[1,1,0] ; encoding: [0x6a,0x18,0x7d,0xd4,0x80,0x05,0x02,0x00]

v_cmp_class_f16 vcc, v128.h, v2.h dpp8:[7,6,5,4,3,2,1,0]
// GFX11: v_cmp_class_f16_e64_dpp vcc, v128.h, v2.h op_sel:[1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x18,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x80,0x77,0x39,0x05]
Expand Down Expand Up @@ -92,10 +92,10 @@ v_cmp_class_f16 vcc, v128.l, v2.l quad_perm:[3,2,1,0]
// GFX11: v_cmp_class_f16_e64_dpp vcc, v128.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x80,0x1b,0x00,0xff]

v_cmp_class_f16 vcc, vcc_hi, v255.h
// GFX11: v_cmp_class_f16_e64 vcc, vcc_hi, v255.h ; encoding: [0x6a,0x10,0x7d,0xd4,0x6b,0xfe,0x03,0x00]
// GFX11: v_cmp_class_f16_e64 vcc, vcc_hi, v255.h op_sel:[0,1,0] ; encoding: [0x6a,0x10,0x7d,0xd4,0x6b,0xfe,0x03,0x00]

v_cmp_class_f16 vcc, vcc_hi, v255.h
// GFX11: v_cmp_class_f16_e64 vcc, vcc_hi, v255.h ; encoding: [0x6a,0x10,0x7d,0xd4,0x6b,0xfe,0x03,0x00]
// GFX11: v_cmp_class_f16_e64 vcc, vcc_hi, v255.h op_sel:[0,1,0] ; encoding: [0x6a,0x10,0x7d,0xd4,0x6b,0xfe,0x03,0x00]

v_cmp_class_f16 vcc, vcc_hi, v255.l
// GFX11: v_cmp_class_f16_e64 vcc, vcc_hi, v255.l ; encoding: [0x6a,0x00,0x7d,0xd4,0x6b,0xfe,0x03,0x00]
Expand All @@ -104,10 +104,10 @@ v_cmp_class_f16 vcc, vcc_hi, v255.l
// GFX11: v_cmp_class_f16_e64 vcc, vcc_hi, v255.l ; encoding: [0x6a,0x00,0x7d,0xd4,0x6b,0xfe,0x03,0x00]

v_cmp_class_f16 vcc, vcc_lo, v255.h
// GFX11: v_cmp_class_f16_e64 vcc, vcc_lo, v255.h ; encoding: [0x6a,0x10,0x7d,0xd4,0x6a,0xfe,0x03,0x00]
// GFX11: v_cmp_class_f16_e64 vcc, vcc_lo, v255.h op_sel:[0,1,0] ; encoding: [0x6a,0x10,0x7d,0xd4,0x6a,0xfe,0x03,0x00]

v_cmp_class_f16 vcc, vcc_lo, v255.h
// GFX11: v_cmp_class_f16_e64 vcc, vcc_lo, v255.h ; encoding: [0x6a,0x10,0x7d,0xd4,0x6a,0xfe,0x03,0x00]
// GFX11: v_cmp_class_f16_e64 vcc, vcc_lo, v255.h op_sel:[0,1,0] ; encoding: [0x6a,0x10,0x7d,0xd4,0x6a,0xfe,0x03,0x00]

v_cmp_class_f16 vcc, vcc_lo, v255.l
// GFX11: v_cmp_class_f16_e64 vcc, vcc_lo, v255.l ; encoding: [0x6a,0x00,0x7d,0xd4,0x6a,0xfe,0x03,0x00]
Expand Down
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