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release/20.x: [X86] Do not combine LRINT and TRUNC (#125848) #125995

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Merged
merged 1 commit into from
Feb 7, 2025

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@llvmbot llvmbot commented Feb 6, 2025

Backport 8c222c1

Requested by: @phoebewang

@llvmbot llvmbot added this to the LLVM 20.X Release milestone Feb 6, 2025
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llvmbot commented Feb 6, 2025

@phoebewang What do you think about merging this PR to the release branch?

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llvmbot commented Feb 6, 2025

@llvm/pr-subscribers-backend-x86

Author: None (llvmbot)

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Backport 8c222c1

Requested by: @phoebewang


Full diff: https://github.com/llvm/llvm-project/pull/125995.diff

2 Files Affected:

  • (modified) llvm/lib/Target/X86/X86ISelLowering.cpp (-5)
  • (modified) llvm/test/CodeGen/X86/lrint-conv-i64.ll (+18)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 8f904209d8a3ad9..627cef9ead7ffac 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -53899,11 +53899,6 @@ static SDValue combineTruncate(SDNode *N, SelectionDAG &DAG,
       return DAG.getNode(X86ISD::MMX_MOVD2W, DL, MVT::i32, BCSrc);
   }
 
-  // Try to combine (trunc (vNi64 (lrint x))) to (vNi32 (lrint x)).
-  if (Src.getOpcode() == ISD::LRINT && VT.getScalarType() == MVT::i32 &&
-      Src.hasOneUse())
-    return DAG.getNode(ISD::LRINT, DL, VT, Src.getOperand(0));
-
   return SDValue();
 }
 
diff --git a/llvm/test/CodeGen/X86/lrint-conv-i64.ll b/llvm/test/CodeGen/X86/lrint-conv-i64.ll
index 01b0af2f807f200..38fa09085e1898d 100644
--- a/llvm/test/CodeGen/X86/lrint-conv-i64.ll
+++ b/llvm/test/CodeGen/X86/lrint-conv-i64.ll
@@ -45,6 +45,24 @@ entry:
   ret i64 %0
 }
 
+define i32 @PR125324(float %x) {
+; SSE-LABEL: PR125324:
+; SSE:       # %bb.0: # %entry
+; SSE-NEXT:    cvtss2si %xmm0, %rax
+; SSE-NEXT:    # kill: def $eax killed $eax killed $rax
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: PR125324:
+; AVX:       # %bb.0: # %entry
+; AVX-NEXT:    vcvtss2si %xmm0, %rax
+; AVX-NEXT:    # kill: def $eax killed $eax killed $rax
+; AVX-NEXT:    retq
+entry:
+  %0 = tail call i64 @llvm.lrint.i64.f32(float %x)
+  %1 = trunc i64 %0 to i32
+  ret i32 %1
+}
+
 declare i64 @llvm.lrint.i64.f32(float) nounwind readnone
 declare i64 @llvm.lrint.i64.f64(double) nounwind readnone
 declare i64 @llvm.lrint.i64.f80(x86_fp80) nounwind readnone

@phoebewang phoebewang requested a review from topperc February 6, 2025 05:06
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LGTM

Per to discussions in llvm#125324, most participants are opposed to this
optimization. So remove the combination to address the concerns.

Fixes llvm#125324

(cherry picked from commit 8c222c1)
@tstellar tstellar merged commit 454d7c1 into llvm:release/20.x Feb 7, 2025
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github-actions bot commented Feb 7, 2025

@phoebewang (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR.

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6 participants