[RISCV][Sema] Add feature check for target attribute to VSETVL intrinsics #126064
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
…sics This fixes the target attribute issue for vsetvl and vsetvlmax intrinsics. Fixes llvm#125154
llvmbot
added
clang
|
@llvm/pr-subscribers-clang @llvm/pr-subscribers-backend-risc-v Author: Brandon Wu (4vtomat) ChangesThis fixes the target attribute issue for vsetvl and vsetvlmax Full diff: https://github.com/llvm/llvm-project/pull/126064.diff 3 Files Affected:
diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td
index c4d2afe407516c0..c1446a50703266a 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -634,7 +634,6 @@ let HeaderCode =
#define __riscv_vsetvl_e32m4(avl) __builtin_rvv_vsetvli((size_t)(avl), 2, 2)
#define __riscv_vsetvl_e32m8(avl) __builtin_rvv_vsetvli((size_t)(avl), 2, 3)
-#if __riscv_v_elen >= 64
#define __riscv_vsetvl_e8mf8(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 5)
#define __riscv_vsetvl_e16mf4(avl) __builtin_rvv_vsetvli((size_t)(avl), 1, 6)
#define __riscv_vsetvl_e32mf2(avl) __builtin_rvv_vsetvli((size_t)(avl), 2, 7)
@@ -643,7 +642,6 @@ let HeaderCode =
#define __riscv_vsetvl_e64m2(avl) __builtin_rvv_vsetvli((size_t)(avl), 3, 1)
#define __riscv_vsetvl_e64m4(avl) __builtin_rvv_vsetvli((size_t)(avl), 3, 2)
#define __riscv_vsetvl_e64m8(avl) __builtin_rvv_vsetvli((size_t)(avl), 3, 3)
-#endif
#define __riscv_vsetvlmax_e8mf4() __builtin_rvv_vsetvlimax(0, 6)
#define __riscv_vsetvlmax_e8mf2() __builtin_rvv_vsetvlimax(0, 7)
@@ -663,7 +661,6 @@ let HeaderCode =
#define __riscv_vsetvlmax_e32m4() __builtin_rvv_vsetvlimax(2, 2)
#define __riscv_vsetvlmax_e32m8() __builtin_rvv_vsetvlimax(2, 3)
-#if __riscv_v_elen >= 64
#define __riscv_vsetvlmax_e8mf8() __builtin_rvv_vsetvlimax(0, 5)
#define __riscv_vsetvlmax_e16mf4() __builtin_rvv_vsetvlimax(1, 6)
#define __riscv_vsetvlmax_e32mf2() __builtin_rvv_vsetvlimax(2, 7)
@@ -672,7 +669,6 @@ let HeaderCode =
#define __riscv_vsetvlmax_e64m2() __builtin_rvv_vsetvlimax(3, 1)
#define __riscv_vsetvlmax_e64m4() __builtin_rvv_vsetvlimax(3, 2)
#define __riscv_vsetvlmax_e64m8() __builtin_rvv_vsetvlimax(3, 3)
-#endif
}] in
def vsetvl_macro: RVVHeader;
diff --git a/clang/lib/Sema/SemaRISCV.cpp b/clang/lib/Sema/SemaRISCV.cpp
index 163f7129a7b42bb..222addf877365c9 100644
--- a/clang/lib/Sema/SemaRISCV.cpp
+++ b/clang/lib/Sema/SemaRISCV.cpp
@@ -623,13 +623,37 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo &TI,
}
}
+ auto checkVsetvl = [&](unsigned SEWOffset,
+ unsigned LMULOffset) -> bool {
+ const FunctionDecl *FD = SemaRef.getCurFunctionDecl();
+ llvm::StringMap<bool> FunctionFeatureMap;
+ Context.getFunctionFeatureMap(FunctionFeatureMap, FD);
+ llvm::APSInt SEWResult;
+ llvm::APSInt LMULResult;
+ if (SemaRef.BuiltinConstantArg(TheCall, SEWOffset, SEWResult) ||
+ SemaRef.BuiltinConstantArg(TheCall, LMULOffset, LMULResult))
+ return true;
+ int SEWValue = SEWResult.getSExtValue();
+ int LMULValue = LMULResult.getSExtValue();
+ if (((SEWValue == 0 && LMULValue == 5) || // e8mf8
+ (SEWValue == 1 && LMULValue == 6) || // e16mf4
+ (SEWValue == 2 && LMULValue == 7) || // e32mf2
+ (SEWValue == 3 && LMULValue == 0) || // e64m1
+ (SEWValue == 3 && LMULValue == 1) || // e64m2
+ (SEWValue == 3 && LMULValue == 2) || // e64m4
+ (SEWValue == 3 && LMULValue == 3)) && // e64m8
+ (!TI.hasFeature("zve64x") && !FunctionFeatureMap.lookup("zve64x")))
+ return Diag(TheCall->getBeginLoc(),
+ diag::err_riscv_builtin_requires_extension)
+ << /* IsExtension */ true << TheCall->getSourceRange() << "zve64x";
+ return SemaRef.BuiltinConstantArgRange(TheCall, SEWOffset, 0, 3) ||
+ CheckLMUL(TheCall, LMULOffset);
+ };
switch (BuiltinID) {
case RISCVVector::BI__builtin_rvv_vsetvli:
- return SemaRef.BuiltinConstantArgRange(TheCall, 1, 0, 3) ||
- CheckLMUL(TheCall, 2);
+ return checkVsetvl(1, 2);
case RISCVVector::BI__builtin_rvv_vsetvlimax:
- return SemaRef.BuiltinConstantArgRange(TheCall, 0, 0, 3) ||
- CheckLMUL(TheCall, 1);
+ return checkVsetvl(0, 1);
case RISCVVector::BI__builtin_rvv_vget_v: {
ASTContext::BuiltinVectorTypeInfo ResVecInfo =
Context.getBuiltinVectorTypeInfo(cast<BuiltinType>(
diff --git a/clang/test/CodeGen/RISCV/riscv-func-attr-target.c b/clang/test/CodeGen/RISCV/riscv-func-attr-target.c
index 3e9c1d9229a66bf..cd83876ec5f9077 100644
--- a/clang/test/CodeGen/RISCV/riscv-func-attr-target.c
+++ b/clang/test/CodeGen/RISCV/riscv-func-attr-target.c
@@ -65,6 +65,20 @@ void test_rvv_f64_type_w_zve64d() {
vfloat64m1_t v;
}
+__attribute__((target("arch=+v")))
+int test_vsetvl_e64m1(unsigned avl) {
+// CHECK-LABEL: test_vsetvl_e64m1
+// CHECK-SAME: #13
+ return __riscv_vsetvl_e64m1(avl);
+}
+
+__attribute__((target("arch=+v")))
+int test_vsetvlmax_e64m1() {
+// CHECK-LABEL: test_vsetvlmax_e64m1
+// CHECK-SAME: #13
+ return __riscv_vsetvlmax_e64m1();
+}
+
//.
// CHECK: attributes #0 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zaamo,+zalrsc,+zifencei,+zmmul,-relax,-zbb,-zfa" }
// CHECK: attributes #1 = { {{.*}}"target-cpu"="rocket-rv64" "target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zbb,-zfa" "tune-cpu"="generic-rv64" }
|
|
✅ With the latest revision this PR passed the C/C++ code formatter. |
topperc
reviewed
Feb 6, 2025
topperc
reviewed
Feb 6, 2025
tclin914
reviewed
Feb 7, 2025
clang/lib/Sema/SemaRISCV.cpp
Outdated
| (SEWValue == 3 && LMULValue == 1) || // e64m2 | ||
| (SEWValue == 3 && LMULValue == 2) || // e64m4 | ||
| (SEWValue == 3 && LMULValue == 3)) && // e64m8 | ||
| (!TI.hasFeature("zve64x") && !FunctionFeatureMap.lookup("zve64x"))) |
There was a problem hiding this comment.
Should we check for the feature zvl64b?
There was a problem hiding this comment.
The requirements for supported vtypes is a function of ELEN not VLEN. A Zvl64b+Zve32x implementation may support e8,mf8, e16,mf4, e32,mf2 but it is not required by the spec so any code that used it would not be portable. The intrinsics API explicitly excluded these for that reason.
wangpc-pp
reviewed
Feb 7, 2025
|
Ping~ |
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/4/builds/5623 Here is the relevant piece of the build log for the reference |
frederik-h
pushed a commit
to frederik-h/llvm-project
that referenced
this pull request
Mar 18, 2025
…sics (llvm#126064) This fixes the target attribute issue for vsetvl and vsetvlmax intrinsics. Fixes llvm#125154
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
This fixes the target attribute issue for vsetvl and vsetvlmax
intrinsics.
Fixes #125154