[RISCV] Improve Errors for X1/X5/X1X5 Reg Classes

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

@@ -247,8 +247,16 @@ def GPR : GPRRegisterClass<(add (sequence "X%u", 10, 17),
                                 (sequence "X%u", 0, 4))>;
 
 def GPRX0 : GPRRegisterClass<(add X0)>;
-def GPRX1 : GPRRegisterClass<(add X1)>;
-def GPRX5 : GPRRegisterClass<(add X5)>;
+
+def GPRX1 : GPRRegisterClass<(add X1)> {
+  let DiagnosticType = "InvalidRegClassGPRX1";
+  let DiagnosticString = "register must be ra (x1)";
+}
+
+def GPRX5 : GPRRegisterClass<(add X5)> {
+  let DiagnosticType = "InvalidRegClassGPRX5";
+  let DiagnosticString = "register must be t0 (x5)";
+}
 
 def GPRNoX0 : GPRRegisterClass<(sub GPR, X0)>;
 
@@ -282,7 +290,10 @@ def SP : GPRRegisterClass<(add X2)>;
 def SR07 : GPRRegisterClass<(add (sequence "X%u", 8, 9),
                                  (sequence "X%u", 18, 23))>;
 
-def GPRX1X5 :  GPRRegisterClass<(add X1, X5)>;
+def GPRX1X5 :  GPRRegisterClass<(add X1, X5)> {
+  let DiagnosticType = "InvalidRegClassGPRX1X5";
+  let DiagnosticString = "register must be ra or t0 (x1 or x5)";
+}
 
 //===----------------------------------------------------------------------===//
 // Even-Odd GPR Pairs

llvm/test/MC/RISCV/zicfiss-invalid.s

@@ -0,0 +1,19 @@
+# RUN: not llvm-mc %s -triple=riscv32 -mattr=+experimental-zicfiss,+zcmop,+c -M no-aliases -show-encoding \
+# RUN:     2>&1 | FileCheck -check-prefixes=CHECK-ERR %s
+# RUN: not llvm-mc %s -triple=riscv64 -mattr=+experimental-zicfiss,+zcmop,+c -M no-aliases -show-encoding \
+# RUN:     2>&1 | FileCheck -check-prefixes=CHECK-ERR %s
+
+# CHECK-ERR: error: register must be ra or t0 (x1 or x5)
+sspopchk a1
+
+# CHECK-ERR: error: register must be ra (x1)
+c.sspush t0
+
+# CHECK-ERR: error: register must be t0 (x5)
+c.sspopchk ra
+
+# CHECK-ERR: error: register must be ra or t0 (x1 or x5)
+sspush a0
+
+# CHECK-ERR: error: invalid operand for instruction
+ssrdp zero