[Hexagon] Fix typos discovered by codespell (NFC) #126233
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Found using https://github.com/codespell-project/codespell codespell Hexagon --ignore-words-list=CarryIn,CreateOr,ORE,COPYs,ArchVer,predicable,UE,MIs,isNT,Vor,CountR,DUM,GEs,AddD,ToI,CopyIn,TheI,TotalIn,vor,MOne,contigious,Contigious --write-changes
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@llvm/pr-subscribers-backend-hexagon Author: Sudharsan Veeravalli (svs-quic) ChangesFound using https://github.com/codespell-project/codespell Patch is 30.25 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/126233.diff 27 Files Affected:
diff --git a/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp b/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
index e99858372a3c081..20881de1d94f4ee 100644
--- a/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
+++ b/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
@@ -74,7 +74,7 @@ static cl::opt<bool> WarnSignedMismatch(
cl::init(false));
static cl::opt<bool> WarnNoncontigiousRegister(
"mwarn-noncontigious-register",
- cl::desc("Warn for register names that arent contigious"), cl::init(true));
+ cl::desc("Warn for register names that aren't contigious"), cl::init(true));
static cl::opt<bool> ErrorNoncontigiousRegister(
"merror-noncontigious-register",
cl::desc("Error for register names that aren't contigious"),
@@ -1330,7 +1330,7 @@ unsigned HexagonAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
return Match_InvalidOperand;
}
-// FIXME: Calls to OutOfRange shoudl propagate failure up to parseStatement.
+// FIXME: Calls to OutOfRange should propagate failure up to parseStatement.
bool HexagonAsmParser::OutOfRange(SMLoc IDLoc, long long Val, long long Max) {
std::string errStr;
raw_string_ostream ES(errStr);
diff --git a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
index 19226759177527d..67d822a67e53c71 100644
--- a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
@@ -2854,7 +2854,7 @@ bool HexagonBitSimplify::runOnMachineFunction(MachineFunction &MF) {
// Recognize loops where the code at the end of the loop matches the code
// before the entry of the loop, and the matching code is such that is can
// be simplified. This pass relies on the bit simplification above and only
-// prepares code in a way that can be handled by the bit simplifcation.
+// prepares code in a way that can be handled by the bit simplification.
//
// This is the motivating testcase (and explanation):
//
diff --git a/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp b/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp
index 90daac736f12677..55e8572f3319813 100644
--- a/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp
@@ -1040,7 +1040,7 @@ unsigned HCE::getDirectRegReplacement(unsigned ExtOpc) const {
// extender. It may be possible for MI to be tweaked to work for a register
// defined with a slightly different value. For example
// ... = L2_loadrub_io Rb, 1
-// can be modifed to be
+// can be modified to be
// ... = L2_loadrub_io Rb', 0
// if Rb' = Rb+1.
// The range for Rb would be [Min+1, Max+1], where [Min, Max] is a range
diff --git a/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp b/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
index f68444c0b8d462b..92374199b2c91ed 100644
--- a/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
@@ -101,7 +101,7 @@ namespace {
// Lattice cell, based on that was described in the W-Z paper on constant
// propagation.
- // Latice cell will be allowed to hold multiple constant values. While
+ // Lattice cell will be allowed to hold multiple constant values. While
// multiple values would normally indicate "bottom", we can still derive
// some useful information from them. For example, comparison X > 0
// could be folded if all the values in the cell associated with X are
@@ -795,7 +795,7 @@ void MachineConstPropagator::visitUsesOf(unsigned Reg) {
LLVM_DEBUG(dbgs() << "Visiting uses of " << printReg(Reg, &MCE.TRI)
<< Cells.get(Reg) << '\n');
for (MachineInstr &MI : MRI->use_nodbg_instructions(Reg)) {
- // Do not process non-executable instructions. They can become exceutable
+ // Do not process non-executable instructions. They can become executable
// later (via a flow-edge in the work queue). In such case, the instruc-
// tion will be visited at that time.
if (!InstrExec.count(&MI))
diff --git a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
index 99ac0c346d0c0d3..7b681fa44f4d6b9 100644
--- a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
@@ -385,7 +385,7 @@ bool HexagonCopyToCombine::isSafeToMoveTogether(MachineInstr &I1,
return true;
}
-/// findPotentialNewifiableTFRs - Finds tranfers that feed stores that could be
+/// findPotentialNewifiableTFRs - Finds transfers that feed stores that could be
/// newified. (A use of a 64 bit register define can not be newified)
void
HexagonCopyToCombine::findPotentialNewifiableTFRs(MachineBasicBlock &BB) {
diff --git a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
index 06f6abe5bf8476d..02e2d670ebee27b 100644
--- a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
@@ -720,7 +720,7 @@ bool HexagonExpandCondsets::split(MachineInstr &MI,
}
}
- // First, create the two invididual conditional transfers, and add each
+ // First, create the two individual conditional transfers, and add each
// of them to the live intervals information. Do that first and then remove
// the old instruction from live intervals.
MachineInstr *TfrT =
diff --git a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
index 933474634924045..743991447ad1fb8 100644
--- a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
@@ -825,7 +825,7 @@ CountValue *HexagonHardwareLoops::computeCount(MachineLoop *Loop,
// a computation of it into the preheader.
// If the induction variable bump is not a power of 2, quit.
- // Othwerise we'd need a general integer division.
+ // Otherwise we'd need a general integer division.
if (!isPowerOf2_64(std::abs(IVBump)))
return nullptr;
@@ -1398,10 +1398,10 @@ bool HexagonHardwareLoops::phiMayWrapOrUnderflow(
/// counter if it is <= 1. We only need to perform this analysis if the
/// initial value is a register.
///
-/// This function assumes the initial value may underfow unless proven
+/// This function assumes the initial value may underflow unless proven
/// otherwise. If the type is signed, then we don't care because signed
/// underflow is undefined. We attempt to prove the initial value is not
-/// zero by perfoming a crude analysis of the loop counter. This function
+/// zero by performing a crude analysis of the loop counter. This function
/// checks if the initial value is used in any comparison prior to the loop
/// and, if so, assumes the comparison is a range check. This is inexact,
/// but will catch the simple cases.
diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp
index a1956092efbdee7..7635eb634380c8f 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp
@@ -1984,7 +1984,7 @@ SmallVector<uint32_t, 8> HvxSelector::getPerfectCompletions(ShuffleMask SM,
// same as in P. This implies that P == Q.
// There can be a situation where there are more entries with the same
- // bits set than there are set bits (e.g. value 9 occuring more than 2
+ // bits set than there are set bits (e.g. value 9 occurring more than 2
// times). In such cases it will be impossible to complete this to a
// perfect shuffle.
SmallVector<uint32_t, 8> Sorted(Worklist);
@@ -1995,7 +1995,7 @@ SmallVector<uint32_t, 8> HvxSelector::getPerfectCompletions(ShuffleMask SM,
while (++I != E && P == Sorted[I])
++Count;
if ((unsigned)llvm::popcount(P) < Count) {
- // Reset all occurences of P, if there are more occurrences of P
+ // Reset all occurrences of P, if there are more occurrences of P
// than there are bits in P.
llvm::replace(Worklist, P, 0U);
}
@@ -2223,7 +2223,7 @@ OpRef HvxSelector::perfect(ShuffleMask SM, OpRef Va, ResultStack &Results) {
// V6_vdeal{b,h}
// V6_vshuff{b,h}
- // V6_vshufoe{b,h} those are quivalent to vshuffvdd(..,{1,2})
+ // V6_vshufoe{b,h} those are equivalent to vshuffvdd(..,{1,2})
// V6_vshuffvdd (V6_vshuff)
// V6_dealvdd (V6_vdeal)
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index 12ca0c505bd06a2..1a7667fe42fbca1 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -814,7 +814,7 @@ SDValue HexagonTargetLowering::LowerFormalArguments(
// stack where the return value will be stored. For Hexagon, the location on
// caller's stack is passed only when the struct size is smaller than (and
// equal to) 8 bytes. If not, no address will be passed into callee and
- // callee return the result direclty through R0/R1.
+ // callee return the result directly through R0/R1.
auto NextSingleReg = [] (const TargetRegisterClass &RC, unsigned Reg) {
switch (RC.getID()) {
case Hexagon::IntRegsRegClassID:
@@ -979,7 +979,7 @@ HexagonTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
// If first Vararg register is odd, add 4 bytes to start of
// saved register area to point to the first register location.
// This is because the saved register area has to be 8 byte aligned.
- // Incase of an odd start register, there will be 4 bytes of padding in
+ // In case of an odd start register, there will be 4 bytes of padding in
// the beginning of saved register area. If all registers area used up,
// the following condition will handle it correctly.
SDValue SavedRegAreaStartFrameIndex =
@@ -1321,7 +1321,7 @@ HexagonTargetLowering::GetDynamicTLSAddr(SelectionDAG &DAG, SDValue Chain,
}
//
-// Lower using the intial executable model for TLS addresses
+// Lower using the initial executable model for TLS addresses
//
SDValue
HexagonTargetLowering::LowerToTLSInitialExecModel(GlobalAddressSDNode *GA,
@@ -3320,7 +3320,7 @@ HexagonTargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo());
Chain = DAG.getCopyToReg(Chain, dl, OffsetReg, Offset);
- // Not needed we already use it as explict input to EH_RETURN.
+ // Not needed we already use it as explicit input to EH_RETURN.
// MF.getRegInfo().addLiveOut(OffsetReg);
return DAG.getNode(HexagonISD::EH_RETURN, dl, MVT::Other, Chain);
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
index 816e063f8dbbe5f..deffe6369df170a 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
@@ -2400,7 +2400,7 @@ HexagonTargetLowering::VectorPair
HexagonTargetLowering::emitHvxAddWithOverflow(SDValue A, SDValue B,
const SDLoc &dl, bool Signed, SelectionDAG &DAG) const {
// Compute A+B, return {A+B, O}, where O = vector predicate indicating
- // whether an overflow has occured.
+ // whether an overflow has occurred.
MVT ResTy = ty(A);
assert(ResTy == ty(B));
MVT PredTy = MVT::getVectorVT(MVT::i1, ResTy.getVectorNumElements());
@@ -2911,7 +2911,7 @@ HexagonTargetLowering::CreateTLWrapper(SDValue Op, SelectionDAG &DAG) const {
#ifndef NDEBUG
Op.dump(&DAG);
#endif
- llvm_unreachable("Unepected operator");
+ llvm_unreachable("Unexpected operator");
}
const SDLoc &dl(Op);
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
index c54114513ac03c8..bd6ece19f9ad7db 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -2240,7 +2240,7 @@ bool HexagonInstrInfo::isDependent(const MachineInstr &ProdMI,
return false;
}
-// Returns true if the instruction is alread a .cur.
+// Returns true if the instruction is already a .cur.
bool HexagonInstrInfo::isDotCurInst(const MachineInstr &MI) const {
switch (MI.getOpcode()) {
case Hexagon::V6_vL32b_cur_pi:
@@ -3860,7 +3860,7 @@ int HexagonInstrInfo::getDotNewPredJumpOp(const MachineInstr &MI,
int HexagonInstrInfo::getDotNewPredOp(const MachineInstr &MI,
const MachineBranchProbabilityInfo *MBPI) const {
switch (MI.getOpcode()) {
- // Condtional Jumps
+ // Conditional Jumps
case Hexagon::J2_jumpt:
case Hexagon::J2_jumpf:
return getDotNewPredJumpOp(MI, MBPI);
@@ -4325,7 +4325,7 @@ unsigned HexagonInstrInfo::getInstrTimingClassLatency(
/// operand latency. But it may not be possible for instructions with variable
/// number of defs / uses.
///
-/// This is a raw interface to the itinerary that may be directly overriden by
+/// This is a raw interface to the itinerary that may be directly overridden by
/// a target. Use computeOperandLatency to get the best estimate of latency.
std::optional<unsigned> HexagonInstrInfo::getOperandLatency(
const InstrItineraryData *ItinData, const MachineInstr &DefMI,
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h
index 6bfb6d42095badd..2debdde78bfb29b 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h
@@ -145,7 +145,7 @@ class HexagonInstrInfo : public HexagonGenInstrInfo {
/// Second variant of isProfitableToIfCvt. This one
/// checks for the case where two basic blocks from true and false path
- /// of a if-then-else (diamond) are predicated on mutally exclusive
+ /// of a if-then-else (diamond) are predicated on mutually exclusive
/// predicates, where the probability of the true path being taken is given
/// by Probability, and Confidence is a measure of our confidence that it
/// will be properly predicted.
@@ -307,8 +307,9 @@ class HexagonInstrInfo : public HexagonGenInstrInfo {
/// operand latency. But it may not be possible for instructions with variable
/// number of defs / uses.
///
- /// This is a raw interface to the itinerary that may be directly overriden by
- /// a target. Use computeOperandLatency to get the best estimate of latency.
+ /// This is a raw interface to the itinerary that may be directly overridden
+ /// by a target. Use computeOperandLatency to get the best estimate of
+ /// latency.
std::optional<unsigned> getOperandLatency(const InstrItineraryData *ItinData,
const MachineInstr &DefMI,
unsigned DefIdx,
diff --git a/llvm/lib/Target/Hexagon/HexagonLoopAlign.cpp b/llvm/lib/Target/Hexagon/HexagonLoopAlign.cpp
index 7d4c9eacbabfbf5..8ebead8a41c9050 100644
--- a/llvm/lib/Target/Hexagon/HexagonLoopAlign.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonLoopAlign.cpp
@@ -49,7 +49,7 @@ static cl::opt<uint32_t> TinyLoopBndlAlignLimit(
static cl::opt<uint32_t>
LoopEdgeThreshold("hexagon-loop-edge-threshold", cl::Hidden, cl::init(7500),
- cl::desc("Set hexagon loop align edge theshold"));
+ cl::desc("Set hexagon loop align edge threshold"));
namespace llvm {
FunctionPass *createHexagonLoopAlign();
diff --git a/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp b/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp
index 36c52dfe81d5ab1..ee01ebc4daa260a 100644
--- a/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp
@@ -13,10 +13,10 @@
// Having said that, we should re-attempt to pull this earlier at some point
// in future.
-// The basic approach looks for sequence of predicated jump, compare instruciton
-// that genereates the predicate and, the feeder to the predicate. Once it finds
+// The basic approach looks for sequence of predicated jump, compare instruction
+// that generates the predicate and, the feeder to the predicate. Once it finds
// all, it collapses compare and jump instruction into a new value jump
-// intstructions.
+// instructions.
//
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp b/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp
index 693649c2e8e581b..66832f31e94ed9a 100644
--- a/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp
@@ -152,10 +152,10 @@ bool HexagonOptAddrMode::hasRepForm(MachineInstr &MI, unsigned TfrDefR) {
}
if (HII->getAddrMode(MI) == HexagonII::BaseRegOffset)
- // Tranform to Absolute plus register offset.
+ // Transform to Absolute plus register offset.
return (HII->changeAddrMode_rr_ur(MI) >= 0);
else if (HII->getAddrMode(MI) == HexagonII::BaseImmOffset)
- // Tranform to absolute addressing mode.
+ // Transform to absolute addressing mode.
return (HII->changeAddrMode_io_abs(MI) >= 0);
return false;
@@ -163,7 +163,7 @@ bool HexagonOptAddrMode::hasRepForm(MachineInstr &MI, unsigned TfrDefR) {
// Check if addasl instruction can be removed. This is possible only
// if it's feeding to only load/store instructions with base + register
-// offset as these instruction can be tranformed to use 'absolute plus
+// offset as these instruction can be transformed to use 'absolute plus
// shifted register offset'.
// ex:
// Rs = ##foo
@@ -551,7 +551,7 @@ bool HexagonOptAddrMode::processAddBases(NodeAddr<StmtNode *> AddSN,
return Changed;
ProcessedAddiInsts.insert(AddMI);
- // Get the base register that would be shared by other Addi Intructions
+ // Get the base register that would be shared by other Addi Instructions
Register BaseReg = AddMI->getOperand(1).getReg();
// Store a list of all Addi instructions that share the above common base
@@ -638,7 +638,7 @@ bool HexagonOptAddrMode::processAddBases(NodeAddr<StmtNode *> AddSN,
NewOffset = CurrentMIImmOp.getImm() - FirstReachedMIImmOp.getImm();
- // This is the first occuring Addi, so skip modifying this
+ // This is the first occurring Addi, so skip modifying this
if (CurrentMI == FirstReachedMI) {
continue;
}
@@ -1084,7 +1084,7 @@ bool HexagonOptAddrMode::processBlock(NodeAddr<BlockNode *> BA) {
// Analyze all uses of 'add'. If the output of 'add' is used as an address
// in the base+immediate addressing mode load/store instructions, see if
- // they can be updated to use the immediate value as an offet. Thus,
+ // they can be updated to use the immediate value as an offset. Thus,
// providing us the opportunity to eliminate 'add'.
// Ex: Rx= add(Rt,#12)
// memw(Rx+#0) = Rs
diff --git a/llvm/lib/Target/Hexagon/HexagonPeephole.cpp b/llvm/lib/Target/Hexagon/HexagonPeephole.cpp
index 532a8401f9dac33..349f2f1d91dc9b5 100644
--- a/llvm/lib/Target/Hexagon/HexagonPeephole.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonPeephole.cpp
@@ -1,4 +1,4 @@
-//===-- HexagonPeephole.cpp - Hexagon Peephole Optimiztions ---------------===//
+//===-- HexagonPeephole.cpp - Hexagon Peephole Optimizations --------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
diff --git a/llvm/lib/Target/Hexagon/HexagonPseudo.td b/llvm/lib/Target/Hexagon/HexagonPseudo.td
index 94b6af024d280e9..c2f38a9ccf5b315 100644
--- a/llvm/lib/Target/Hexagon/HexagonPseudo.td
+++ b/llvm/lib/Target/Hexagon/HexagonPseudo.td
@@ -185,7 +185,7 @@ def PS_call_stk : T_Call<"">;
// This pseudo instruction is used to replace int_hexagon_instrprof_custom intrinsic
// with a call to custom handler passed as the first argument to the intrinsic.
-// Pleae Note:
+// Please Note:
// 1) The call to the custom handler is being treated as a special one as the
// callee is responsible for saving and restoring all the registers it needs
// to modify. This includes caller saved registers as well as r0-r5 argument
diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
index b340bfee3d7e216..ffe9ce750bf5090 100644
--- a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
@@ -686,7 +686,7 @@ bool HexagonSubtarget::isBestZeroLatency(SUnit *Src, SUnit *Dst,
restoreLa...
[truncated]
|
quic-santdas
approved these changes
Feb 10, 2025
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/73/builds/13019 Here is the relevant piece of the build log for the reference |
Icohedron
pushed a commit
to Icohedron/llvm-project
that referenced
this pull request
Feb 11, 2025
Found using https://github.com/codespell-project/codespell ``` codespell Hexagon --write-changes \ --ignore-words-list=CarryIn,CreateOr,ORE,COPYs,ArchVer,predicable,UE,MIs,isNT,Vor,CountR,DUM,GEs,AddD,ToI, \ CopyIn,TheI,TotalIn,vor,MOne,contigious,Contigious ```
joaosaffran
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that referenced
this pull request
Feb 14, 2025
Found using https://github.com/codespell-project/codespell ``` codespell Hexagon --write-changes \ --ignore-words-list=CarryIn,CreateOr,ORE,COPYs,ArchVer,predicable,UE,MIs,isNT,Vor,CountR,DUM,GEs,AddD,ToI, \ CopyIn,TheI,TotalIn,vor,MOne,contigious,Contigious ```
androm3da
reviewed
Feb 18, 2025
Comment on lines
75
to
78
| static cl::opt<bool> WarnNoncontigiousRegister( | ||
| "mwarn-noncontigious-register", | ||
| cl::desc("Warn for register names that arent contigious"), cl::init(true)); | ||
| cl::desc("Warn for register names that aren't contigious"), cl::init(true)); | ||
| static cl::opt<bool> ErrorNoncontigiousRegister( |
There was a problem hiding this comment.
It fixed "aren't" but it left "contigious"? We should also s/contigious/contiguous/ while we're fixing typos.
There was a problem hiding this comment.
I had left out contigious since it is also a part of the variable name. Wasn't sure if we wanted to make changes to variable names.
--ignore-words-list=CarryIn,CreateOr,ORE,COPYs,ArchVer,predicable,UE,MIs,isNT,Vor,CountR,DUM,GEs,AddD,ToI,
CopyIn,TheI,TotalIn,vor,MOne,contigious,Contigious
There was a problem hiding this comment.
Okay, I see. Well - IMO we should fix it at some point.
sivan-shani
pushed a commit
to sivan-shani/llvm-project
that referenced
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Feb 24, 2025
Found using https://github.com/codespell-project/codespell ``` codespell Hexagon --write-changes \ --ignore-words-list=CarryIn,CreateOr,ORE,COPYs,ArchVer,predicable,UE,MIs,isNT,Vor,CountR,DUM,GEs,AddD,ToI, \ CopyIn,TheI,TotalIn,vor,MOne,contigious,Contigious ```
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Found using https://github.com/codespell-project/codespell