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[AMDGPU] - Fix non-deterministic compile issue #126271

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Merged
merged 1 commit into from
Feb 10, 2025

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dstutt
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@dstutt dstutt commented Feb 7, 2025

4ce1f9079d4d3 [AMDGPU] Allow rematerialization of instructions with virtual register uses (#124327)
made changes that require an ordered traversal of a DenseMap. Changing it to MapVector which
respects insertion order.

4ce1f9079d4d3 [AMDGPU] Allow rematerialization of instructions with virtual register uses (llvm#124327)
made changes that require an ordered traversal of a DenseMap. Changing it to MapVector which
respects insertion order.
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llvmbot commented Feb 7, 2025

@llvm/pr-subscribers-backend-amdgpu

Author: David Stuttard (dstutt)

Changes

4ce1f9079d4d3 [AMDGPU] Allow rematerialization of instructions with virtual register uses (#124327)
made changes that require an ordered traversal of a DenseMap. Changing it to MapVector which
respects insertion order.


Full diff: https://github.com/llvm/llvm-project/pull/126271.diff

1 Files Affected:

  • (modified) llvm/lib/Target/AMDGPU/GCNSchedStrategy.h (+1-1)
diff --git a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.h b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
index 7d3e63df43da60..e3da8d30056293 100644
--- a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
+++ b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
@@ -442,7 +442,7 @@ class PreRARematStage : public GCNSchedStage {
 
   // Map a trivially rematerializable def to a list of regions at MinOccupancy
   // that has the defined reg as a live-in.
-  DenseMap<MachineInstr *, SmallVector<unsigned, 4>> RematDefToLiveInRegions;
+  MapVector<MachineInstr *, SmallVector<unsigned, 4>> RematDefToLiveInRegions;
 
   // Collect all trivially rematerializable VGPR instructions with a single def
   // and single use outside the defining block into RematerializableInsts.

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jayfoad commented Feb 7, 2025

Sounds reasonable, but I don't immediately see anything in #124327 which iterates over RematDefToLiveInRegions. How and where does that happen?

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dstutt commented Feb 7, 2025

Sounds reasonable, but I don't immediately see anything in #124327 which iterates over RematDefToLiveInRegions. How and where does that happen?

There's an iteration over RematDefToLiveInRegions in sinkTriviallyRematInsts - which pre-dates the changes in #124327
My assumption is that the change enabled more rematerialization - and that's highlighted this pre-existing issue that probably didn't trigger very often before.
Note that we're only seeing the issue on 2 test pipelines out of 10k+ and only for one asic variant.

The resulting code is going to be functionally correct in both cases, so this only gets picked up when we specifically check for non-determinism.

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There's an iteration over RematDefToLiveInRegions in sinkTriviallyRematInsts - which pre-dates the changes in #124327
My assumption is that the change enabled more rematerialization - and that's highlighted this pre-existing issue that probably didn't trigger very often before.

This is correct -- thanks

@dstutt dstutt merged commit 30e7c10 into llvm:main Feb 10, 2025
10 checks passed
Icohedron pushed a commit to Icohedron/llvm-project that referenced this pull request Feb 11, 2025
4ce1f9079d4d3 [AMDGPU] Allow rematerialization of instructions with
virtual register uses (llvm#124327)
made changes that require an ordered traversal of a DenseMap. Changing
it to MapVector which
respects insertion order.
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4 participants