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[RISCV] Refactor tablegen classes to push common values down to VPseudoBinaryM. NFC #126339

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Feb 8, 2025
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[RISCV] Refactor tablegen classes to push common values down to VPseudoBinaryM. NFC #126339

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90 changes: 40 additions & 50 deletions llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
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Original file line number Diff line number Diff line change
Expand Up @@ -2136,23 +2136,6 @@ multiclass VPseudoBinaryRoundingMode<VReg RetClass,
}


multiclass VPseudoBinaryM<VReg RetClass,
VReg Op1Class,
DAGOperand Op2Class,
LMULInfo MInfo,
string Constraint = "",
bits<2> TargetConstraintType = 1,
bit Commutable = 0> {
let VLMul = MInfo.value, isCommutable = Commutable in {
def "_" # MInfo.MX : VPseudoBinaryNoMask<RetClass, Op1Class, Op2Class,
Constraint, TargetConstraintType>;
let ForceTailAgnostic = true in
def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMOutMask<RetClass, Op1Class,
Op2Class, Constraint, TargetConstraintType>,
RISCVMaskedPseudo<MaskIdx=3>;
}
}

multiclass VPseudoBinaryEmul<VReg RetClass,
VReg Op1Class,
DAGOperand Op2Class,
Expand Down Expand Up @@ -2633,28 +2616,35 @@ multiclass PseudoVEXT_VF8 {
// lowest-numbered part of the source register group".
// With LMUL<=1 the source and dest occupy a single register so any overlap
// is in the lowest-numbered part.
multiclass VPseudoBinaryM_VV<LMULInfo m, bits<2> TargetConstraintType = 1,
bit Commutable = 0> {
defm _VV : VPseudoBinaryM<VR, m.vrclass, m.vrclass, m,
multiclass VPseudoBinaryM<DAGOperand Op2Class, LMULInfo m, bit Commutable = 0> {
let VLMul = m.value, isCommutable = Commutable in {
def "_" # m.MX :
VPseudoBinaryNoMask<VR, m.vrclass, Op2Class,
!if(!ge(m.octuple, 16), "@earlyclobber $rd", ""),
TargetConstraintType = 2>;
let ForceTailAgnostic = true in
def "_" # m.MX # "_MASK" :
VPseudoBinaryMOutMask<VR, m.vrclass, Op2Class,
!if(!ge(m.octuple, 16), "@earlyclobber $rd", ""),
TargetConstraintType, Commutable=Commutable>;
TargetConstraintType = 2>,
RISCVMaskedPseudo<MaskIdx=3>;
}
}

multiclass VPseudoBinaryM_VX<LMULInfo m, bits<2> TargetConstraintType = 1> {
defm "_VX" :
VPseudoBinaryM<VR, m.vrclass, GPR, m,
!if(!ge(m.octuple, 16), "@earlyclobber $rd", ""), TargetConstraintType>;
multiclass VPseudoBinaryM_VV<LMULInfo m, bit Commutable = 0> {
defm _VV : VPseudoBinaryM<m.vrclass, m, Commutable=Commutable>;
}

multiclass VPseudoBinaryM_VF<LMULInfo m, FPR_Info f, bits<2> TargetConstraintType = 1> {
defm "_V" # f.FX :
VPseudoBinaryM<VR, m.vrclass, f.fprclass, m,
!if(!ge(m.octuple, 16), "@earlyclobber $rd", ""), TargetConstraintType>;
multiclass VPseudoBinaryM_VX<LMULInfo m> {
defm _VX : VPseudoBinaryM<GPR, m>;
}

multiclass VPseudoBinaryM_VI<LMULInfo m, bits<2> TargetConstraintType = 1> {
defm _VI : VPseudoBinaryM<VR, m.vrclass, simm5, m,
!if(!ge(m.octuple, 16), "@earlyclobber $rd", ""), TargetConstraintType>;
multiclass VPseudoBinaryM_VF<LMULInfo m, FPR_Info f> {
defm "_V" # f.FX : VPseudoBinaryM<f.fprclass, m>;
}

multiclass VPseudoBinaryM_VI<LMULInfo m> {
defm _VI : VPseudoBinaryM<simm5, m>;
}

multiclass VPseudoVGTR_VV_VX_VI {
Expand Down Expand Up @@ -3397,34 +3387,44 @@ multiclass VPseudoVWMAC_VV_VF_BF_RM {
multiclass VPseudoVCMPM_VV_VX_VI<bit Commutable = 0> {
foreach m = MxList in {
defvar mx = m.MX;
defm "" : VPseudoBinaryM_VV<m, TargetConstraintType=2, Commutable=Commutable>,
defm "" : VPseudoBinaryM_VV<m, Commutable=Commutable>,
SchedBinary<"WriteVICmpV", "ReadVICmpV", "ReadVICmpV", mx>;
defm "" : VPseudoBinaryM_VX<m, TargetConstraintType=2>,
defm "" : VPseudoBinaryM_VX<m>,
SchedBinary<"WriteVICmpX", "ReadVICmpV", "ReadVICmpX", mx>;
defm "" : VPseudoBinaryM_VI<m, TargetConstraintType=2>,
defm "" : VPseudoBinaryM_VI<m>,
SchedUnary<"WriteVICmpI", "ReadVICmpV", mx>;
}
}

multiclass VPseudoVCMPM_VV_VX {
foreach m = MxList in {
defvar mx = m.MX;
defm "" : VPseudoBinaryM_VV<m, TargetConstraintType=2>,
defm "" : VPseudoBinaryM_VV<m>,
SchedBinary<"WriteVICmpV", "ReadVICmpV", "ReadVICmpV", mx>;
defm "" : VPseudoBinaryM_VX<m, TargetConstraintType=2>,
defm "" : VPseudoBinaryM_VX<m>,
SchedBinary<"WriteVICmpX", "ReadVICmpV", "ReadVICmpX", mx>;
}
}

multiclass VPseudoVCMPM_VX_VI {
foreach m = MxList in {
defvar mx = m.MX;
defm "" : VPseudoBinaryM_VX<m>,
SchedBinary<"WriteVICmpX", "ReadVICmpV", "ReadVICmpX", mx>;
defm "" : VPseudoBinaryM_VI<m>,
SchedUnary<"WriteVICmpI", "ReadVICmpV", mx>;
}
}

multiclass VPseudoVCMPM_VV_VF {
foreach m = MxListF in {
defm "" : VPseudoBinaryM_VV<m, TargetConstraintType=2>,
defm "" : VPseudoBinaryM_VV<m>,
SchedBinary<"WriteVFCmpV", "ReadVFCmpV", "ReadVFCmpV", m.MX>;
}

foreach f = FPList in {
foreach m = f.MxList in {
defm "" : VPseudoBinaryM_VF<m, f, TargetConstraintType=2>,
defm "" : VPseudoBinaryM_VF<m, f>,
SchedBinary<"WriteVFCmpF", "ReadVFCmpV", "ReadVFCmpF", m.MX>;
}
}
Expand All @@ -3433,22 +3433,12 @@ multiclass VPseudoVCMPM_VV_VF {
multiclass VPseudoVCMPM_VF {
foreach f = FPList in {
foreach m = f.MxList in {
defm "" : VPseudoBinaryM_VF<m, f, TargetConstraintType=2>,
defm "" : VPseudoBinaryM_VF<m, f>,
SchedBinary<"WriteVFCmpF", "ReadVFCmpV", "ReadVFCmpF", m.MX>;
}
}
}

multiclass VPseudoVCMPM_VX_VI {
foreach m = MxList in {
defvar mx = m.MX;
defm "" : VPseudoBinaryM_VX<m, TargetConstraintType=2>,
SchedBinary<"WriteVICmpX", "ReadVICmpV", "ReadVICmpX", mx>;
defm "" : VPseudoBinaryM_VI<m, TargetConstraintType=2>,
SchedUnary<"WriteVICmpI", "ReadVICmpV", mx>;
}
}

multiclass VPseudoVRED_VS {
foreach m = MxList in {
defvar mx = m.MX;
Expand Down