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[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes #126608

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Merged
merged 2 commits into from
Feb 12, 2025
Merged

[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes #126608

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d2857c4
[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes
preames Feb 10, 2025
911915c
Merge branch 'main' into pr-riscv-generic-schedule-for-regpressure
preames Feb 12, 2025
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21 changes: 15 additions & 6 deletions llvm/lib/Target/RISCV/RISCVProcessors.td
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Original file line number Diff line number Diff line change
Expand Up @@ -88,21 +88,30 @@ class RISCVTuneProcessorModel<string n,

defvar GenericTuneFeatures = [TuneOptimizedNF2SegmentLoadStore];

// Adjust the default cost model to enable all heuristics, not just latency
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I think it worths a standalone file just like in #120712. As discussed, we may add a generic in-order scheduling model.

// In particular, this enables register pressure heustics which are very
// important for high LMUL vector code, and have little negative impact
// on other configurations,
def GenericModel : SchedMachineModel {
let MicroOpBufferSize = 1;
let CompleteModel = 0;
}

def GENERIC_RV32 : RISCVProcessorModel<"generic-rv32",
NoSchedModel,
GenericModel,
[Feature32Bit,
FeatureStdExtI],
GenericTuneFeatures>,
GenericTuneInfo;
def GENERIC_RV64 : RISCVProcessorModel<"generic-rv64",
NoSchedModel,
GenericModel,
[Feature64Bit,
FeatureStdExtI],
GenericTuneFeatures>,
GenericTuneInfo;
// Support generic for compatibility with other targets. The triple will be used
// to change to the appropriate rv32/rv64 version.
def GENERIC : RISCVTuneProcessorModel<"generic", NoSchedModel>, GenericTuneInfo;
def GENERIC : RISCVTuneProcessorModel<"generic", GenericModel>, GenericTuneInfo;

def MIPS_P8700 : RISCVProcessorModel<"mips-p8700",
MIPSP8700Model,
Expand Down Expand Up @@ -496,7 +505,7 @@ def TENSTORRENT_ASCALON_D8 : RISCVProcessorModel<"tt-ascalon-d8",
TunePostRAScheduler]>;

def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1",
NoSchedModel,
GenericModel,
[Feature64Bit,
FeatureStdExtI,
FeatureStdExtZifencei,
Expand Down Expand Up @@ -556,7 +565,7 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
TuneShiftedZExtWFusion]>;

def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60",
NoSchedModel,
GenericModel,
!listconcat(RVA22S64Features,
[FeatureStdExtV,
FeatureStdExtSscofpmf,
Expand All @@ -581,7 +590,7 @@ def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60",
}

def RP2350_HAZARD3 : RISCVProcessorModel<"rp2350-hazard3",
NoSchedModel,
GenericModel,
[Feature32Bit,
FeatureStdExtI,
FeatureStdExtM,
Expand Down
40 changes: 20 additions & 20 deletions llvm/test/CodeGen/RISCV/GlobalISel/add-imm.ll
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Expand Up @@ -212,30 +212,30 @@ define i64 @add64_accept(i64 %a) nounwind {
define void @add32_reject() nounwind {
; RV32I-LABEL: add32_reject:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a0, %hi(ga)
; RV32I-NEXT: lui a1, %hi(gb)
; RV32I-NEXT: lw a2, %lo(ga)(a0)
; RV32I-NEXT: lw a3, %lo(gb)(a1)
; RV32I-NEXT: lui a4, 1
; RV32I-NEXT: addi a4, a4, -1096
; RV32I-NEXT: add a2, a2, a4
; RV32I-NEXT: add a3, a3, a4
; RV32I-NEXT: sw a2, %lo(ga)(a0)
; RV32I-NEXT: sw a3, %lo(gb)(a1)
; RV32I-NEXT: lui a0, 1
; RV32I-NEXT: lui a1, %hi(ga)
; RV32I-NEXT: lui a2, %hi(gb)
; RV32I-NEXT: lw a3, %lo(ga)(a1)
; RV32I-NEXT: lw a4, %lo(gb)(a2)
; RV32I-NEXT: addi a0, a0, -1096
; RV32I-NEXT: add a3, a3, a0
; RV32I-NEXT: add a0, a4, a0
; RV32I-NEXT: sw a3, %lo(ga)(a1)
; RV32I-NEXT: sw a0, %lo(gb)(a2)
; RV32I-NEXT: ret
;
; RV64I-LABEL: add32_reject:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a0, %hi(ga)
; RV64I-NEXT: lui a1, %hi(gb)
; RV64I-NEXT: lw a2, %lo(ga)(a0)
; RV64I-NEXT: lw a3, %lo(gb)(a1)
; RV64I-NEXT: lui a4, 1
; RV64I-NEXT: addi a4, a4, -1096
; RV64I-NEXT: add a2, a2, a4
; RV64I-NEXT: add a3, a3, a4
; RV64I-NEXT: sw a2, %lo(ga)(a0)
; RV64I-NEXT: sw a3, %lo(gb)(a1)
; RV64I-NEXT: lui a0, 1
; RV64I-NEXT: lui a1, %hi(ga)
; RV64I-NEXT: lui a2, %hi(gb)
; RV64I-NEXT: lw a3, %lo(ga)(a1)
; RV64I-NEXT: lw a4, %lo(gb)(a2)
; RV64I-NEXT: addi a0, a0, -1096
; RV64I-NEXT: add a3, a3, a0
; RV64I-NEXT: add a0, a4, a0
; RV64I-NEXT: sw a3, %lo(ga)(a1)
; RV64I-NEXT: sw a0, %lo(gb)(a2)
; RV64I-NEXT: ret
%1 = load i32, ptr @ga, align 4
%2 = load i32, ptr @gb, align 4
Expand Down
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