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[TargetLowering] Add a new function getNullPtrValue #126665

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[TargetLowering] Add a new function getNullPtrValue #126665

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7 changes: 7 additions & 0 deletions llvm/include/llvm/CodeGen/TargetLowering.h
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Expand Up @@ -5659,6 +5659,13 @@ class TargetLowering : public TargetLoweringBase {
LoadSDNode *OriginalLoad,
SelectionDAG &DAG) const;

/// Return the value of nullptr. In most cases, nullptr is a zero-value
/// constant with the corresponding pointer type. However, this is not always
/// the case. For certain address spaces on some targets, it could be a value
/// like ~0U.
virtual SDValue getNullPtrValue(unsigned AS, const SDLoc &DL,
SelectionDAG &DAG) const;

private:
SDValue foldSetCCWithAnd(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
const SDLoc &DL, DAGCombinerInfo &DCI) const;
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3 changes: 1 addition & 2 deletions llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
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Expand Up @@ -1807,8 +1807,7 @@ SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {

if (isa<ConstantPointerNull>(C)) {
unsigned AS = V->getType()->getPointerAddressSpace();
return DAG.getConstant(0, getCurSDLoc(),
TLI.getPointerTy(DAG.getDataLayout(), AS));
return TLI.getNullPtrValue(AS, getCurSDLoc(), DAG);
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ConstantPointerNull currently means a bitpattern 0. It does not mean a known invalid or sentinel pointer.

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@shiltian shiltian Feb 11, 2025 •
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I don't believe that is the case. For example,

%6 = icmp eq ptr addrspace(5) %5, null

If you check operand(1), it is ptr addrspace(5) null, which is recognized as ConstantPointerNull. Unless you’re suggesting that ptr addrspace(5) null might not be a valid or sentinel pointer (or should not be recognized as ConstantPointerNull), while addrspacecast (ptr null to ptr addrspace(5)) is, then InstCombine is handling this incorrectly by treating them as equivalent.

https://godbolt.org/z/1vrcvWfMz

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In addition, the document suggests that it is "a constant pointer value that points to null". My reading is, it is a nullptr. I don't see where to solely treat it as 0.

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I'm not sure what your godbolt link is trying to show, it doesn't have an addrspace cast?

Here you can see that InstCombine does not fold addrspacecast of null: https://godbolt.org/z/jrq8a8vez There is no assumption that a zero value in one address space maps to a zero value in another.

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Yeah I think I made a mistake here.

}

if (match(C, m_VScale()))
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5 changes: 5 additions & 0 deletions llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
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Expand Up @@ -12188,3 +12188,8 @@ SDValue TargetLowering::scalarizeExtractedVectorLoad(EVT ResultVT,

return Load;
}

SDValue TargetLowering::getNullPtrValue(unsigned AS, const SDLoc &DL,
SelectionDAG &DAG) const {
return DAG.getConstant(0, DL, getPointerTy(DAG.getDataLayout(), AS));
}
9 changes: 9 additions & 0 deletions llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
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Expand Up @@ -6050,3 +6050,12 @@ bool AMDGPUTargetLowering::isReassocProfitable(MachineRegisterInfo &MRI,
Register N0, Register N1) const {
return MRI.hasOneNonDBGUse(N0); // FIXME: handle regbanks
}

SDValue AMDGPUTargetLowering::getNullPtrValue(unsigned AS, const SDLoc &DL,
SelectionDAG &DAG) const {
if (AS == AMDGPUAS::PRIVATE_ADDRESS || AS == AMDGPUAS::LOCAL_ADDRESS) {
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I believe we already have one of these in TargetMachine

return DAG.getConstant(0xffffffff, DL,
getPointerTy(DAG.getDataLayout(), AS));
}
return TargetLowering::getNullPtrValue(AS, DL, DAG);
}
3 changes: 3 additions & 0 deletions llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
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Expand Up @@ -387,6 +387,9 @@ class AMDGPUTargetLowering : public TargetLowering {
MVT getFenceOperandTy(const DataLayout &DL) const override {
return MVT::i32;
}

SDValue getNullPtrValue(unsigned AS, const SDLoc &DL,
SelectionDAG &DAG) const override;
};

namespace AMDGPUISD {
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72 changes: 37 additions & 35 deletions llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
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Expand Up @@ -521,11 +521,12 @@ define amdgpu_kernel void @introduced_copy_to_sgpr(i64 %arg, i32 %arg1, i32 %arg
; GFX908-NEXT: s_waitcnt lgkmcnt(0)
; GFX908-NEXT: v_cvt_f32_u32_e32 v0, s3
; GFX908-NEXT: s_sub_i32 s8, 0, s3
; GFX908-NEXT: v_cvt_f32_f16_e32 v17, s7
; GFX908-NEXT: v_mov_b32_e32 v19, 0
; GFX908-NEXT: v_cvt_f32_f16_e32 v18, s7
; GFX908-NEXT: v_mov_b32_e32 v17, 0
; GFX908-NEXT: v_rcp_iflag_f32_e32 v2, v0
; GFX908-NEXT: v_mov_b32_e32 v0, 0
; GFX908-NEXT: v_mov_b32_e32 v1, 0
; GFX908-NEXT: v_mov_b32_e32 v20, -1
; GFX908-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
; GFX908-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX908-NEXT: v_readfirstlane_b32 s10, v2
Expand All @@ -544,7 +545,7 @@ define amdgpu_kernel void @introduced_copy_to_sgpr(i64 %arg, i32 %arg1, i32 %arg
; GFX908-NEXT: s_cmp_ge_u32 s2, s3
; GFX908-NEXT: s_cselect_b32 s8, s10, s8
; GFX908-NEXT: s_lshr_b32 s7, s7, 16
; GFX908-NEXT: v_cvt_f32_f16_e32 v18, s7
; GFX908-NEXT: v_cvt_f32_f16_e32 v19, s7
; GFX908-NEXT: s_lshl_b64 s[2:3], s[0:1], 5
; GFX908-NEXT: s_lshl_b64 s[12:13], s[8:9], 5
; GFX908-NEXT: s_lshl_b64 s[10:11], s[4:5], 5
Expand Down Expand Up @@ -611,37 +612,37 @@ define amdgpu_kernel void @introduced_copy_to_sgpr(i64 %arg, i32 %arg1, i32 %arg
; GFX908-NEXT: ; => This Inner Loop Header: Depth=2
; GFX908-NEXT: s_add_u32 s20, s18, s7
; GFX908-NEXT: s_addc_u32 s21, s19, s9
; GFX908-NEXT: global_load_dword v21, v19, s[20:21] offset:-12 glc
; GFX908-NEXT: global_load_dword v22, v17, s[20:21] offset:-12 glc
; GFX908-NEXT: s_waitcnt vmcnt(0)
; GFX908-NEXT: global_load_dword v20, v19, s[20:21] offset:-8 glc
; GFX908-NEXT: global_load_dword v21, v17, s[20:21] offset:-8 glc
; GFX908-NEXT: s_waitcnt vmcnt(0)
; GFX908-NEXT: global_load_dword v12, v19, s[20:21] offset:-4 glc
; GFX908-NEXT: global_load_dword v12, v17, s[20:21] offset:-4 glc
; GFX908-NEXT: s_waitcnt vmcnt(0)
; GFX908-NEXT: global_load_dword v12, v19, s[20:21] glc
; GFX908-NEXT: global_load_dword v12, v17, s[20:21] glc
; GFX908-NEXT: s_waitcnt vmcnt(0)
; GFX908-NEXT: ds_read_b64 v[12:13], v19
; GFX908-NEXT: ds_read_b64 v[12:13], v20
; GFX908-NEXT: ds_read_b64 v[14:15], v0
; GFX908-NEXT: s_and_b64 vcc, exec, s[0:1]
; GFX908-NEXT: s_waitcnt lgkmcnt(0)
; GFX908-NEXT: s_cbranch_vccnz .LBB3_7
; GFX908-NEXT: ; %bb.6: ; %bb51
; GFX908-NEXT: ; in Loop: Header=BB3_5 Depth=2
; GFX908-NEXT: v_cvt_f32_f16_sdwa v22, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX908-NEXT: v_cvt_f32_f16_sdwa v23, v22 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX908-NEXT: v_cvt_f32_f16_e32 v22, v22
; GFX908-NEXT: v_cvt_f32_f16_sdwa v24, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX908-NEXT: v_cvt_f32_f16_e32 v21, v21
; GFX908-NEXT: v_cvt_f32_f16_sdwa v23, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX908-NEXT: v_cvt_f32_f16_e32 v20, v20
; GFX908-NEXT: v_add_f32_e32 v24, v17, v12
; GFX908-NEXT: v_add_f32_e32 v25, v18, v13
; GFX908-NEXT: v_add_f32_e32 v26, 0, v12
; GFX908-NEXT: v_add_f32_e32 v27, 0, v13
; GFX908-NEXT: v_add_f32_e32 v15, v22, v15
; GFX908-NEXT: v_add_f32_e32 v14, v21, v14
; GFX908-NEXT: v_add_f32_e32 v13, v23, v13
; GFX908-NEXT: v_add_f32_e32 v12, v20, v12
; GFX908-NEXT: v_add_f32_e32 v5, v5, v25
; GFX908-NEXT: v_add_f32_e32 v4, v4, v24
; GFX908-NEXT: v_add_f32_e32 v7, v7, v27
; GFX908-NEXT: v_add_f32_e32 v6, v6, v26
; GFX908-NEXT: v_add_f32_e32 v25, v18, v12
; GFX908-NEXT: v_add_f32_e32 v26, v19, v13
; GFX908-NEXT: v_add_f32_e32 v27, 0, v12
; GFX908-NEXT: v_add_f32_e32 v28, 0, v13
; GFX908-NEXT: v_add_f32_e32 v15, v23, v15
; GFX908-NEXT: v_add_f32_e32 v14, v22, v14
; GFX908-NEXT: v_add_f32_e32 v13, v24, v13
; GFX908-NEXT: v_add_f32_e32 v12, v21, v12
; GFX908-NEXT: v_add_f32_e32 v5, v5, v26
; GFX908-NEXT: v_add_f32_e32 v4, v4, v25
; GFX908-NEXT: v_add_f32_e32 v7, v7, v28
; GFX908-NEXT: v_add_f32_e32 v6, v6, v27
; GFX908-NEXT: v_add_f32_e32 v8, v8, v14
; GFX908-NEXT: v_add_f32_e32 v9, v9, v15
; GFX908-NEXT: v_add_f32_e32 v10, v10, v12
Expand Down Expand Up @@ -686,6 +687,7 @@ define amdgpu_kernel void @introduced_copy_to_sgpr(i64 %arg, i32 %arg1, i32 %arg
; GFX90A-NEXT: v_cvt_f32_u32_e32 v0, s3
; GFX90A-NEXT: s_sub_i32 s8, 0, s3
; GFX90A-NEXT: v_mov_b32_e32 v19, 0
; GFX90A-NEXT: v_mov_b32_e32 v20, -1
; GFX90A-NEXT: v_rcp_iflag_f32_e32 v2, v0
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], 0, 0
; GFX90A-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
Expand Down Expand Up @@ -770,32 +772,32 @@ define amdgpu_kernel void @introduced_copy_to_sgpr(i64 %arg, i32 %arg1, i32 %arg
; GFX90A-NEXT: ; => This Inner Loop Header: Depth=2
; GFX90A-NEXT: s_add_u32 s20, s18, s7
; GFX90A-NEXT: s_addc_u32 s21, s19, s9
; GFX90A-NEXT: global_load_dword v21, v19, s[20:21] offset:-12 glc
; GFX90A-NEXT: global_load_dword v22, v19, s[20:21] offset:-12 glc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: global_load_dword v20, v19, s[20:21] offset:-8 glc
; GFX90A-NEXT: global_load_dword v21, v19, s[20:21] offset:-8 glc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: global_load_dword v14, v19, s[20:21] offset:-4 glc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: global_load_dword v14, v19, s[20:21] glc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: ds_read_b64 v[14:15], v19
; GFX90A-NEXT: ds_read_b64 v[14:15], v20
; GFX90A-NEXT: ds_read_b64 v[16:17], v0
; GFX90A-NEXT: s_and_b64 vcc, exec, s[0:1]
; GFX90A-NEXT: ; kill: killed $sgpr20 killed $sgpr21
; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NEXT: s_cbranch_vccnz .LBB3_7
; GFX90A-NEXT: ; %bb.6: ; %bb51
; GFX90A-NEXT: ; in Loop: Header=BB3_5 Depth=2
; GFX90A-NEXT: v_cvt_f32_f16_sdwa v23, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX90A-NEXT: v_cvt_f32_f16_e32 v22, v21
; GFX90A-NEXT: v_cvt_f32_f16_sdwa v21, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX90A-NEXT: v_cvt_f32_f16_e32 v20, v20
; GFX90A-NEXT: v_pk_add_f32 v[24:25], v[2:3], v[14:15]
; GFX90A-NEXT: v_pk_add_f32 v[26:27], v[14:15], 0 op_sel_hi:[1,0]
; GFX90A-NEXT: v_cvt_f32_f16_sdwa v23, v22 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX90A-NEXT: v_cvt_f32_f16_e32 v22, v22
; GFX90A-NEXT: v_cvt_f32_f16_sdwa v25, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX90A-NEXT: v_cvt_f32_f16_e32 v24, v21
; GFX90A-NEXT: v_pk_add_f32 v[26:27], v[2:3], v[14:15]
; GFX90A-NEXT: v_pk_add_f32 v[28:29], v[14:15], 0 op_sel_hi:[1,0]
; GFX90A-NEXT: v_pk_add_f32 v[16:17], v[22:23], v[16:17]
; GFX90A-NEXT: v_pk_add_f32 v[14:15], v[20:21], v[14:15]
; GFX90A-NEXT: v_pk_add_f32 v[6:7], v[6:7], v[24:25]
; GFX90A-NEXT: v_pk_add_f32 v[8:9], v[8:9], v[26:27]
; GFX90A-NEXT: v_pk_add_f32 v[14:15], v[24:25], v[14:15]
; GFX90A-NEXT: v_pk_add_f32 v[6:7], v[6:7], v[26:27]
; GFX90A-NEXT: v_pk_add_f32 v[8:9], v[8:9], v[28:29]
; GFX90A-NEXT: v_pk_add_f32 v[10:11], v[10:11], v[16:17]
; GFX90A-NEXT: v_pk_add_f32 v[12:13], v[12:13], v[14:15]
; GFX90A-NEXT: s_mov_b64 s[20:21], -1
Expand Down
11 changes: 6 additions & 5 deletions llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
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Expand Up @@ -73,11 +73,12 @@ define amdgpu_kernel void @blender_no_live_segment_at_def_error(<4 x float> %ext
; CHECK-NEXT: s_mov_b32 s38, s36
; CHECK-NEXT: s_mov_b32 s39, s36
; CHECK-NEXT: .LBB0_7: ; %if.end294.i.i
; CHECK-NEXT: v_mov_b32_e32 v0, 0
; CHECK-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:12
; CHECK-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:8
; CHECK-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4
; CHECK-NEXT: buffer_store_dword v0, off, s[0:3], 0
; CHECK-NEXT: v_mov_b32_e32 v0, -1
; CHECK-NEXT: v_mov_b32_e32 v1, 0
; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; CHECK-NEXT: buffer_store_dword v1, off, s[0:3], 0 offset:11
; CHECK-NEXT: buffer_store_dword v1, off, s[0:3], 0 offset:7
; CHECK-NEXT: buffer_store_dword v1, off, s[0:3], 0 offset:3
; CHECK-NEXT: .LBB0_8: ; %kernel_direct_lighting.exit
; CHECK-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x20
; CHECK-NEXT: v_mov_b32_e32 v0, s36
Expand Down
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