[DAGCombiner] Add hasOneUse checks for folding (not (add X, -1)) to (neg X) #126667
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
…neg X) To get more better codegen for AArch with bic, x86 with andn and riscv with andn.
llvmbot
added
backend:AArch64
backend:X86
llvm:SelectionDAG
|
@llvm/pr-subscribers-backend-x86 @llvm/pr-subscribers-backend-aarch64 Author: Jim Lin (tclin914) ChangesTo get more better codegen for AArch with bic, x86 with andn and riscv with andn. Full diff: https://github.com/llvm/llvm-project/pull/126667.diff 4 Files Affected:
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index f4caaf426de6a07..6c663d19675b842 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -9702,7 +9702,7 @@ SDValue DAGCombiner::visitXOR(SDNode *N) {
}
// fold (not (add X, -1)) -> (neg X)
- if (isAllOnesConstant(N1) && N0.getOpcode() == ISD::ADD &&
+ if (isAllOnesConstant(N1) && N0.getOpcode() == ISD::ADD && N0.hasOneUse() &&
isAllOnesOrAllOnesSplat(N0.getOperand(1))) {
return DAG.getNegative(N0.getOperand(0), DL, VT);
}
diff --git a/llvm/test/CodeGen/AArch64/align-down.ll b/llvm/test/CodeGen/AArch64/align-down.ll
index 4b1cdfd2770f676..96e2a5d7d33f781 100644
--- a/llvm/test/CodeGen/AArch64/align-down.ll
+++ b/llvm/test/CodeGen/AArch64/align-down.ll
@@ -54,10 +54,9 @@ define i32 @t2_commutative(i32 %ptr, i32 %alignment) nounwind {
define i32 @t3_extrause0(i32 %ptr, i32 %alignment, ptr %mask_storage) nounwind {
; CHECK-LABEL: t3_extrause0:
; CHECK: // %bb.0:
-; CHECK-NEXT: neg w8, w1
-; CHECK-NEXT: sub w9, w1, #1
-; CHECK-NEXT: and w0, w0, w8
-; CHECK-NEXT: str w9, [x2]
+; CHECK-NEXT: sub w8, w1, #1
+; CHECK-NEXT: bic w0, w0, w8
+; CHECK-NEXT: str w8, [x2]
; CHECK-NEXT: ret
%mask = add i32 %alignment, -1
store i32 %mask, ptr %mask_storage
diff --git a/llvm/test/CodeGen/X86/align-down.ll b/llvm/test/CodeGen/X86/align-down.ll
index 3c64e108e06ddb0..c359c04f527a31f 100644
--- a/llvm/test/CodeGen/X86/align-down.ll
+++ b/llvm/test/CodeGen/X86/align-down.ll
@@ -82,25 +82,40 @@ define i32 @t2_commutative(i32 %ptr, i32 %alignment) nounwind {
; Extra use tests
define i32 @t3_extrause0(i32 %ptr, i32 %alignment, ptr %mask_storage) nounwind {
-; X86-LABEL: t3_extrause0:
-; X86: # %bb.0:
-; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: leal -1(%eax), %edx
-; X86-NEXT: movl %edx, (%ecx)
-; X86-NEXT: negl %eax
-; X86-NEXT: andl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: retl
+; NOBMI-X86-LABEL: t3_extrause0:
+; NOBMI-X86: # %bb.0:
+; NOBMI-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; NOBMI-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; NOBMI-X86-NEXT: decl %eax
+; NOBMI-X86-NEXT: movl %eax, (%ecx)
+; NOBMI-X86-NEXT: notl %eax
+; NOBMI-X86-NEXT: andl {{[0-9]+}}(%esp), %eax
+; NOBMI-X86-NEXT: retl
;
-; X64-LABEL: t3_extrause0:
-; X64: # %bb.0:
-; X64-NEXT: movl %esi, %eax
-; X64-NEXT: leal -1(%rax), %ecx
-; X64-NEXT: movl %ecx, (%rdx)
-; X64-NEXT: negl %eax
-; X64-NEXT: andl %edi, %eax
-; X64-NEXT: # kill: def $eax killed $eax killed $rax
-; X64-NEXT: retq
+; BMI-X86-LABEL: t3_extrause0:
+; BMI-X86: # %bb.0:
+; BMI-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; BMI-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; BMI-X86-NEXT: decl %ecx
+; BMI-X86-NEXT: movl %ecx, (%eax)
+; BMI-X86-NEXT: andnl {{[0-9]+}}(%esp), %ecx, %eax
+; BMI-X86-NEXT: retl
+;
+; NOBMI-X64-LABEL: t3_extrause0:
+; NOBMI-X64: # %bb.0:
+; NOBMI-X64-NEXT: # kill: def $esi killed $esi def $rsi
+; NOBMI-X64-NEXT: leal -1(%rsi), %eax
+; NOBMI-X64-NEXT: movl %eax, (%rdx)
+; NOBMI-X64-NEXT: notl %eax
+; NOBMI-X64-NEXT: andl %edi, %eax
+; NOBMI-X64-NEXT: retq
+;
+; BMI-X64-LABEL: t3_extrause0:
+; BMI-X64: # %bb.0:
+; BMI-X64-NEXT: decl %esi
+; BMI-X64-NEXT: movl %esi, (%rdx)
+; BMI-X64-NEXT: andnl %edi, %esi, %eax
+; BMI-X64-NEXT: retq
%mask = add i32 %alignment, -1
store i32 %mask, ptr %mask_storage
%bias = and i32 %ptr, %mask
diff --git a/llvm/test/CodeGen/X86/not-of-dec.ll b/llvm/test/CodeGen/X86/not-of-dec.ll
index 97906495031234f..29461619ac80557 100644
--- a/llvm/test/CodeGen/X86/not-of-dec.ll
+++ b/llvm/test/CodeGen/X86/not-of-dec.ll
@@ -57,18 +57,17 @@ define i32 @t2_extrause(i32 %alignment, ptr %mask_storage) nounwind {
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: leal -1(%eax), %edx
-; X86-NEXT: movl %edx, (%ecx)
-; X86-NEXT: negl %eax
+; X86-NEXT: decl %eax
+; X86-NEXT: movl %eax, (%ecx)
+; X86-NEXT: notl %eax
; X86-NEXT: retl
;
; X64-LABEL: t2_extrause:
; X64: # %bb.0:
-; X64-NEXT: movl %edi, %eax
-; X64-NEXT: leal -1(%rax), %ecx
-; X64-NEXT: movl %ecx, (%rsi)
-; X64-NEXT: negl %eax
-; X64-NEXT: # kill: def $eax killed $eax killed $rax
+; X64-NEXT: # kill: def $edi killed $edi def $rdi
+; X64-NEXT: leal -1(%rdi), %eax
+; X64-NEXT: movl %eax, (%rsi)
+; X64-NEXT: notl %eax
; X64-NEXT: retq
%mask = add i32 %alignment, -1
store i32 %mask, ptr %mask_storage
|
|
@llvm/pr-subscribers-llvm-selectiondag Author: Jim Lin (tclin914) ChangesTo get more better codegen for AArch with bic, x86 with andn and riscv with andn. Full diff: https://github.com/llvm/llvm-project/pull/126667.diff 4 Files Affected:
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index f4caaf426de6a07..6c663d19675b842 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -9702,7 +9702,7 @@ SDValue DAGCombiner::visitXOR(SDNode *N) {
}
// fold (not (add X, -1)) -> (neg X)
- if (isAllOnesConstant(N1) && N0.getOpcode() == ISD::ADD &&
+ if (isAllOnesConstant(N1) && N0.getOpcode() == ISD::ADD && N0.hasOneUse() &&
isAllOnesOrAllOnesSplat(N0.getOperand(1))) {
return DAG.getNegative(N0.getOperand(0), DL, VT);
}
diff --git a/llvm/test/CodeGen/AArch64/align-down.ll b/llvm/test/CodeGen/AArch64/align-down.ll
index 4b1cdfd2770f676..96e2a5d7d33f781 100644
--- a/llvm/test/CodeGen/AArch64/align-down.ll
+++ b/llvm/test/CodeGen/AArch64/align-down.ll
@@ -54,10 +54,9 @@ define i32 @t2_commutative(i32 %ptr, i32 %alignment) nounwind {
define i32 @t3_extrause0(i32 %ptr, i32 %alignment, ptr %mask_storage) nounwind {
; CHECK-LABEL: t3_extrause0:
; CHECK: // %bb.0:
-; CHECK-NEXT: neg w8, w1
-; CHECK-NEXT: sub w9, w1, #1
-; CHECK-NEXT: and w0, w0, w8
-; CHECK-NEXT: str w9, [x2]
+; CHECK-NEXT: sub w8, w1, #1
+; CHECK-NEXT: bic w0, w0, w8
+; CHECK-NEXT: str w8, [x2]
; CHECK-NEXT: ret
%mask = add i32 %alignment, -1
store i32 %mask, ptr %mask_storage
diff --git a/llvm/test/CodeGen/X86/align-down.ll b/llvm/test/CodeGen/X86/align-down.ll
index 3c64e108e06ddb0..c359c04f527a31f 100644
--- a/llvm/test/CodeGen/X86/align-down.ll
+++ b/llvm/test/CodeGen/X86/align-down.ll
@@ -82,25 +82,40 @@ define i32 @t2_commutative(i32 %ptr, i32 %alignment) nounwind {
; Extra use tests
define i32 @t3_extrause0(i32 %ptr, i32 %alignment, ptr %mask_storage) nounwind {
-; X86-LABEL: t3_extrause0:
-; X86: # %bb.0:
-; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: leal -1(%eax), %edx
-; X86-NEXT: movl %edx, (%ecx)
-; X86-NEXT: negl %eax
-; X86-NEXT: andl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: retl
+; NOBMI-X86-LABEL: t3_extrause0:
+; NOBMI-X86: # %bb.0:
+; NOBMI-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; NOBMI-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; NOBMI-X86-NEXT: decl %eax
+; NOBMI-X86-NEXT: movl %eax, (%ecx)
+; NOBMI-X86-NEXT: notl %eax
+; NOBMI-X86-NEXT: andl {{[0-9]+}}(%esp), %eax
+; NOBMI-X86-NEXT: retl
;
-; X64-LABEL: t3_extrause0:
-; X64: # %bb.0:
-; X64-NEXT: movl %esi, %eax
-; X64-NEXT: leal -1(%rax), %ecx
-; X64-NEXT: movl %ecx, (%rdx)
-; X64-NEXT: negl %eax
-; X64-NEXT: andl %edi, %eax
-; X64-NEXT: # kill: def $eax killed $eax killed $rax
-; X64-NEXT: retq
+; BMI-X86-LABEL: t3_extrause0:
+; BMI-X86: # %bb.0:
+; BMI-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; BMI-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; BMI-X86-NEXT: decl %ecx
+; BMI-X86-NEXT: movl %ecx, (%eax)
+; BMI-X86-NEXT: andnl {{[0-9]+}}(%esp), %ecx, %eax
+; BMI-X86-NEXT: retl
+;
+; NOBMI-X64-LABEL: t3_extrause0:
+; NOBMI-X64: # %bb.0:
+; NOBMI-X64-NEXT: # kill: def $esi killed $esi def $rsi
+; NOBMI-X64-NEXT: leal -1(%rsi), %eax
+; NOBMI-X64-NEXT: movl %eax, (%rdx)
+; NOBMI-X64-NEXT: notl %eax
+; NOBMI-X64-NEXT: andl %edi, %eax
+; NOBMI-X64-NEXT: retq
+;
+; BMI-X64-LABEL: t3_extrause0:
+; BMI-X64: # %bb.0:
+; BMI-X64-NEXT: decl %esi
+; BMI-X64-NEXT: movl %esi, (%rdx)
+; BMI-X64-NEXT: andnl %edi, %esi, %eax
+; BMI-X64-NEXT: retq
%mask = add i32 %alignment, -1
store i32 %mask, ptr %mask_storage
%bias = and i32 %ptr, %mask
diff --git a/llvm/test/CodeGen/X86/not-of-dec.ll b/llvm/test/CodeGen/X86/not-of-dec.ll
index 97906495031234f..29461619ac80557 100644
--- a/llvm/test/CodeGen/X86/not-of-dec.ll
+++ b/llvm/test/CodeGen/X86/not-of-dec.ll
@@ -57,18 +57,17 @@ define i32 @t2_extrause(i32 %alignment, ptr %mask_storage) nounwind {
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: leal -1(%eax), %edx
-; X86-NEXT: movl %edx, (%ecx)
-; X86-NEXT: negl %eax
+; X86-NEXT: decl %eax
+; X86-NEXT: movl %eax, (%ecx)
+; X86-NEXT: notl %eax
; X86-NEXT: retl
;
; X64-LABEL: t2_extrause:
; X64: # %bb.0:
-; X64-NEXT: movl %edi, %eax
-; X64-NEXT: leal -1(%rax), %ecx
-; X64-NEXT: movl %ecx, (%rsi)
-; X64-NEXT: negl %eax
-; X64-NEXT: # kill: def $eax killed $eax killed $rax
+; X64-NEXT: # kill: def $edi killed $edi def $rdi
+; X64-NEXT: leal -1(%rdi), %eax
+; X64-NEXT: movl %eax, (%rsi)
+; X64-NEXT: notl %eax
; X64-NEXT: retq
%mask = add i32 %alignment, -1
store i32 %mask, ptr %mask_storage
|
arsenm
reviewed
Feb 11, 2025
arsenm
approved these changes
Feb 12, 2025
flovent
pushed a commit
to flovent/llvm-project
that referenced
this pull request
Feb 13, 2025
…neg X) (llvm#126667) To get more better codegen for AArch with bic, x86 with andn and riscv with andn.
joaosaffran
pushed a commit
to joaosaffran/llvm-project
that referenced
this pull request
Feb 14, 2025
…neg X) (llvm#126667) To get more better codegen for AArch with bic, x86 with andn and riscv with andn.
sivan-shani
pushed a commit
to sivan-shani/llvm-project
that referenced
this pull request
Feb 24, 2025
…neg X) (llvm#126667) To get more better codegen for AArch with bic, x86 with andn and riscv with andn.
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
To get more better codegen for AArch with bic, x86 with andn and riscv with andn.