Skip to content

[AMDGPU] Remove FeatureForceStoreSC0SC1 #126878

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Feb 19, 2025
Merged

[AMDGPU] Remove FeatureForceStoreSC0SC1 #126878

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
6 changes: 0 additions & 6 deletions llvm/lib/Target/AMDGPU/AMDGPU.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1040,12 +1040,6 @@ def FeatureVALUTransUseHazard : SubtargetFeature<"valu-trans-use-hazard",
"Hazard when TRANS instructions are closely followed by a use of the result"
>;

def FeatureForceStoreSC0SC1 : SubtargetFeature<"force-store-sc0-sc1",
"HasForceStoreSC0SC1",
"true",
"Has SC0 and SC1 on stores"
>;

def FeatureSALUFloatInsts : SubtargetFeature<"salu-float",
"HasSALUFloatInsts",
"true",
Expand Down
3 changes: 0 additions & 3 deletions llvm/lib/Target/AMDGPU/GCNSubtarget.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -246,7 +246,6 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
bool HasMADIntraFwdBug = false;
bool HasVOPDInsts = false;
bool HasVALUTransUseHazard = false;
bool HasForceStoreSC0SC1 = false;
bool HasRequiredExportPriority = false;
bool HasVmemWriteVgprInOrder = false;
bool HasAshrPkInsts = false;
Expand Down Expand Up @@ -1264,8 +1263,6 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,

bool hasCvtScaleForwardingHazard() const { return GFX950Insts; }

bool hasForceStoreSC0SC1() const { return HasForceStoreSC0SC1; }

bool requiresCodeObjectV6() const { return RequiresCOV6; }

bool hasVALUMaskWriteHazard() const { return getGeneration() == GFX11; }
Expand Down
20 changes: 0 additions & 20 deletions llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -359,11 +359,6 @@ class SICacheControl {

/// Virtual destructor to allow derivations to be deleted.
virtual ~SICacheControl() = default;

virtual bool tryForceStoreSC0SC1(const SIMemOpInfo &MOI,
MachineBasicBlock::iterator &MI) const {
return false;
}
};

class SIGfx6CacheControl : public SICacheControl {
Expand Down Expand Up @@ -517,20 +512,6 @@ class SIGfx940CacheControl : public SIGfx90ACacheControl {
bool insertRelease(MachineBasicBlock::iterator &MI, SIAtomicScope Scope,
SIAtomicAddrSpace AddrSpace, bool IsCrossAddrSpaceOrdering,
Position Pos) const override;

bool tryForceStoreSC0SC1(const SIMemOpInfo &MOI,
MachineBasicBlock::iterator &MI) const override {
bool Changed = false;
if (ST.hasForceStoreSC0SC1() &&
(MOI.getInstrAddrSpace() & (SIAtomicAddrSpace::SCRATCH |
SIAtomicAddrSpace::GLOBAL |
SIAtomicAddrSpace::OTHER)) !=
SIAtomicAddrSpace::NONE) {
Changed |= enableSC0Bit(MI);
Changed |= enableSC1Bit(MI);
}
return Changed;
}
};

class SIGfx10CacheControl : public SIGfx7CacheControl {
Expand Down Expand Up @@ -2820,7 +2801,6 @@ bool SIMemoryLegalizer::runOnMachineFunction(MachineFunction &MF) {
Changed |= expandLoad(*MOI, MI);
else if (const auto &MOI = MOA.getStoreInfo(MI)) {
Changed |= expandStore(*MOI, MI);
Changed |= CC->tryForceStoreSC0SC1(*MOI, MI);
} else if (const auto &MOI = MOA.getAtomicFenceInfo(MI))
Changed |= expandAtomicFence(*MOI, MI);
else if (const auto &MOI = MOA.getAtomicCmpxchgOrRmwInfo(MI))
Expand Down