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[AMDGPU] Switch to MF.estimateFunctionSizeInBytes() #127246

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[AMDGPU] Switch to MF.estimateFunctionSizeInBytes() #127246

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2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -8977,7 +8977,7 @@ unsigned SIInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo(), &ST);
}
default:
if (MI.isMetaInstruction())
if (MI.isMetaInstruction() || MI.isDebugInstr())
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I'd expect DescSize to be correct for debug insts

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I am not sure downstream staging branch has adequate testing for this assumption.

return 0;
return DescSize;
}
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31 changes: 4 additions & 27 deletions llvm/lib/Target/AMDGPU/SIProgramInfo.cpp
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Expand Up @@ -202,32 +202,9 @@ const MCExpr *SIProgramInfo::getPGMRSrc2(CallingConv::ID CC,
return MCConstantExpr::create(0, Ctx);
}

uint64_t SIProgramInfo::getFunctionCodeSize(const MachineFunction &MF) {
if (CodeSizeInBytes.has_value())
return *CodeSizeInBytes;
uint64_t SIProgramInfo::getFunctionCodeSize(MachineFunction &MF) {
if (!CodeSizeInBytes.has_value())
CodeSizeInBytes = MF.estimateFunctionSizeInBytes();

const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
const SIInstrInfo *TII = STM.getInstrInfo();

uint64_t CodeSize = 0;

for (const MachineBasicBlock &MBB : MF) {
// The amount of padding to align code can be both underestimated and
// overestimated. In case of inline asm used getInstSizeInBytes() will
// return a maximum size of a single instruction, where the real size may
// differ. At this point CodeSize may be already off.
CodeSize = alignTo(CodeSize, MBB.getAlignment());

for (const MachineInstr &MI : MBB) {
// TODO: CodeSize should account for multiple functions.

if (MI.isMetaInstruction())
continue;

CodeSize += TII->getInstSizeInBytes(MI);
}
}

CodeSizeInBytes = CodeSize;
return CodeSize;
return *CodeSizeInBytes;
}
2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/SIProgramInfo.h
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Expand Up @@ -101,7 +101,7 @@ struct LLVM_EXTERNAL_VISIBILITY SIProgramInfo {
void reset(const MachineFunction &MF);

// Get function code size and cache the value.
uint64_t getFunctionCodeSize(const MachineFunction &MF);
uint64_t getFunctionCodeSize(MachineFunction &MF);

/// Compute the value of the ComputePGMRsrc1 register.
const MCExpr *getComputePGMRSrc1(const GCNSubtarget &ST,
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6 changes: 3 additions & 3 deletions llvm/test/CodeGen/AMDGPU/code-size-estimate.mir
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Expand Up @@ -61,7 +61,7 @@ body: |
# CHECK: s_barrier ; encoding: [0x00,0x00,0x8a,0xbf]
# CHECK: .p2align 3
# CHECK: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
# CHECK: ; codeLenInByte = 20
# CHECK: ; codeLenInByte = 24
---
name: align8
tracksRegLiveness: true
Expand All @@ -83,7 +83,7 @@ body: |
# CHECK: s_barrier ; encoding: [0x00,0x00,0x8a,0xbf]
# CHECK: .p2align 4
# CHECK: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
# CHECK: ; codeLenInByte = 20
# CHECK: ; codeLenInByte = 32
---
name: align16
tracksRegLiveness: true
Expand All @@ -105,7 +105,7 @@ body: |
# CHECK: s_barrier ; encoding: [0x00,0x00,0x8a,0xbf]
# CHECK: .p2align 5
# CHECK: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
# CHECK: ; codeLenInByte = 36
# CHECK: ; codeLenInByte = 64
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It is rebased. Now it shows how this method can largely overestimate code size.

---
name: align32
tracksRegLiveness: true
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