Skip to content

[X86][FP16] Adding lowerings for FP16 ISD::LRINT and ISD::LLRINT #127382

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Feb 22, 2025
Merged

[X86][FP16] Adding lowerings for FP16 ISD::LRINT and ISD::LLRINT #127382

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
51 changes: 44 additions & 7 deletions llvm/lib/Target/X86/X86ISelLowering.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -735,6 +735,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setOperationAction(ISD::FCANONICALIZE, MVT::f16, Custom);
setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f32, Custom);
setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f64, Custom);
setOperationAction(ISD::LRINT, MVT::f16, Expand);
setOperationAction(ISD::LLRINT, MVT::f16, Expand);

setLibcallName(RTLIB::FPROUND_F32_F16, "__truncsfhf2");
setLibcallName(RTLIB::FPEXT_F16_F32, "__extendhfsf2");
Expand Down Expand Up @@ -2312,6 +2314,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setOperationAction(ISD::FMINIMUMNUM, MVT::f16, Custom);
setOperationAction(ISD::FP_EXTEND, MVT::f32, Legal);
setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f32, Legal);
setOperationAction(ISD::LRINT, MVT::f16, Legal);
setOperationAction(ISD::LLRINT, MVT::f16, Legal);

setCondCodeAction(ISD::SETOEQ, MVT::f16, Expand);
setCondCodeAction(ISD::SETUNE, MVT::f16, Expand);
Expand Down Expand Up @@ -2359,6 +2363,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setOperationAction(ISD::FMAXIMUM, MVT::v32f16, Custom);
setOperationAction(ISD::FMINIMUMNUM, MVT::v32f16, Custom);
setOperationAction(ISD::FMAXIMUMNUM, MVT::v32f16, Custom);
setOperationAction(ISD::LRINT, MVT::v32f16, Legal);
setOperationAction(ISD::LLRINT, MVT::v8f16, Legal);
}

if (Subtarget.hasVLX()) {
Expand Down Expand Up @@ -2413,6 +2419,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setOperationAction(ISD::FMAXIMUM, MVT::v16f16, Custom);
setOperationAction(ISD::FMINIMUMNUM, MVT::v16f16, Custom);
setOperationAction(ISD::FMAXIMUMNUM, MVT::v16f16, Custom);
setOperationAction(ISD::LRINT, MVT::v8f16, Legal);
setOperationAction(ISD::LRINT, MVT::v16f16, Legal);
}
}

Expand Down Expand Up @@ -34055,8 +34063,15 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
case ISD::LRINT:
if (N->getValueType(0) == MVT::v2i32) {
SDValue Src = N->getOperand(0);
if (Src.getValueType() == MVT::v2f64)
Results.push_back(DAG.getNode(X86ISD::CVTP2SI, dl, MVT::v4i32, Src));
if (Subtarget.hasFP16() && Src.getValueType() == MVT::v2f16) {
Src = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f16, Src,
DAG.getUNDEF(MVT::v2f16));
Src = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8f16, Src,
DAG.getUNDEF(MVT::v4f16));
} else if (Src.getValueType() != MVT::v2f64) {
return;
}
Results.push_back(DAG.getNode(X86ISD::CVTP2SI, dl, MVT::v4i32, Src));
return;
}
[[fallthrough]];
Expand Down Expand Up @@ -53640,13 +53655,35 @@ static SDValue combineLRINT_LLRINT(SDNode *N, SelectionDAG &DAG,
EVT SrcVT = Src.getValueType();
SDLoc DL(N);

if (!Subtarget.hasDQI() || !Subtarget.hasVLX() || VT != MVT::v2i64 ||
SrcVT != MVT::v2f32)
const TargetLowering &TLI = DAG.getTargetLoweringInfo();

// Let legalize expand this if it isn't a legal type yet.
if (!TLI.isTypeLegal(VT))
return SDValue();

if ((SrcVT.getScalarType() == MVT::f16 && !Subtarget.hasFP16()) ||
(SrcVT.getScalarType() == MVT::f32 && !Subtarget.hasDQI()))
return SDValue();

return DAG.getNode(X86ISD::CVTP2SI, DL, VT,
DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32, Src,
DAG.getUNDEF(SrcVT)));
if (SrcVT == MVT::v2f16) {
SrcVT = MVT::v4f16;
Src = DAG.getNode(ISD::CONCAT_VECTORS, DL, SrcVT, Src,
DAG.getUNDEF(MVT::v2f16));
}

if (SrcVT == MVT::v4f16) {
SrcVT = MVT::v8f16;
Src = DAG.getNode(ISD::CONCAT_VECTORS, DL, SrcVT, Src,
DAG.getUNDEF(MVT::v4f16));
} else if (SrcVT == MVT::v2f32) {
SrcVT = MVT::v4f32;
Src = DAG.getNode(ISD::CONCAT_VECTORS, DL, SrcVT, Src,
DAG.getUNDEF(MVT::v2f32));
} else {
return SDValue();
}

return DAG.getNode(X86ISD::CVTP2SI, DL, VT, Src);
}

/// Attempt to pre-truncate inputs to arithmetic ops if it will simplify
Expand Down
33 changes: 33 additions & 0 deletions llvm/lib/Target/X86/X86InstrAVX512.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -13143,6 +13143,26 @@ defm VCVTTPH2UQQ : avx512_cvttph2qq<0x78, "vcvttph2uqq", X86any_cvttp2ui,
SchedWriteCvtPS2DQ>, T_MAP5, PD,
EVEX_CD8<16, CD8VQ>;

let Predicates = [HasFP16, HasVLX] in {
def : Pat<(v8i16 (lrint (v8f16 VR128X:$src))), (VCVTPH2WZ128rr VR128X:$src)>;
def : Pat<(v8i16 (lrint (loadv8f16 addr:$src))), (VCVTPH2WZ128rm addr:$src)>;
def : Pat<(v16i16 (lrint (v16f16 VR256X:$src))), (VCVTPH2WZ256rr VR256X:$src)>;
def : Pat<(v16i16 (lrint (loadv16f16 addr:$src))), (VCVTPH2WZ256rm addr:$src)>;
def : Pat<(v8i32 (lrint (v8f16 VR128X:$src))), (VCVTPH2DQZ256rr VR128X:$src)>;
def : Pat<(v8i32 (lrint (loadv8f16 addr:$src))), (VCVTPH2DQZ256rm addr:$src)>;
}

let Predicates = [HasFP16] in {
def : Pat<(v32i16 (lrint (v32f16 VR512:$src))), (VCVTPH2WZrr VR512:$src)>;
def : Pat<(v32i16 (lrint (loadv32f16 addr:$src))), (VCVTPH2WZrm addr:$src)>;
def : Pat<(v16i32 (lrint (v16f16 VR256X:$src))), (VCVTPH2DQZrr VR256X:$src)>;
def : Pat<(v16i32 (lrint (loadv16f16 addr:$src))), (VCVTPH2DQZrm addr:$src)>;
def : Pat<(v8i64 (lrint (v8f16 VR128X:$src))), (VCVTPH2QQZrr VR128X:$src)>;
def : Pat<(v8i64 (lrint (loadv8f16 addr:$src))), (VCVTPH2QQZrm addr:$src)>;
def : Pat<(v8i64 (llrint (v8f16 VR128X:$src))), (VCVTPH2QQZrr VR128X:$src)>;
def : Pat<(v8i64 (llrint (loadv8f16 addr:$src))), (VCVTPH2QQZrm addr:$src)>;
}

// Convert Signed/Unsigned Quardword to Half
multiclass avx512_cvtqq2ph<bits<8> opc, string OpcodeStr, SDPatternOperator OpNode,
SDPatternOperator MaskOpNode, SDNode OpNodeRnd,
Expand Down Expand Up @@ -13269,6 +13289,19 @@ defm VCVTTSH2USI64Z: avx512_cvt_s_all<0x78, "vcvttsh2usi", f16x_info, i64x_info,
any_fp_to_uint, X86cvtts2UInt, X86cvtts2UIntSAE, WriteCvtSS2I,
"{q}", HasFP16>, T_MAP5, XS, REX_W, EVEX_CD8<16, CD8VT1>;

let Predicates = [HasFP16] in {
def : Pat<(i16 (lrint FR16:$src)), (EXTRACT_SUBREG (VCVTTSH2SIZrr FR16:$src), sub_16bit)>;
def : Pat<(i32 (lrint FR16:$src)), (VCVTTSH2SIZrr FR16:$src)>;
def : Pat<(i32 (lrint (loadf16 addr:$src))), (VCVTTSH2SIZrm addr:$src)>;
}

let Predicates = [HasFP16, In64BitMode] in {
def : Pat<(i64 (lrint FR16:$src)), (VCVTTSH2SI64Zrr FR16:$src)>;
def : Pat<(i64 (lrint (loadf16 addr:$src))), (VCVTTSH2SI64Zrm addr:$src)>;
def : Pat<(i64 (llrint FR16:$src)), (VCVTTSH2SI64Zrr FR16:$src)>;
def : Pat<(i64 (llrint (loadf16 addr:$src))), (VCVTTSH2SI64Zrm addr:$src)>;
}

let Predicates = [HasFP16] in {
defm VCVTSI2SHZ : avx512_vcvtsi_common<0x2A, X86SintToFp, X86SintToFpRnd, WriteCvtI2SS, GR32,
v8f16x_info, i32mem, loadi32, "cvtsi2sh", "l">,
Expand Down
Loading
Loading