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[SelectionDAG] Utilizing target hook convertSelectOfConstantsToMath for SelectwithConstant #127599

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Feb 25, 2025
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[SelectionDAG] Utilizing target hook convertSelectOfConstantsToMath for SelectwithConstant #127599

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3 changes: 2 additions & 1 deletion llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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Expand Up @@ -28191,7 +28191,8 @@ SDValue DAGCombiner::SimplifySelectCC(const SDLoc &DL, SDValue N0, SDValue N1,
if ((Fold || Swap) &&
TLI.getBooleanContents(CmpOpVT) ==
TargetLowering::ZeroOrOneBooleanContent &&
(!LegalOperations || TLI.isOperationLegal(ISD::SETCC, CmpOpVT))) {
(!LegalOperations || TLI.isOperationLegal(ISD::SETCC, CmpOpVT)) &&
TLI.convertSelectOfConstantsToMath(VT)) {

if (Swap) {
CC = ISD::getSetCCInverse(CC, CmpOpVT);
Expand Down
78 changes: 40 additions & 38 deletions llvm/test/CodeGen/AArch64/bfis-in-loop.ll
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Expand Up @@ -13,25 +13,26 @@ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
define i64 @bfis_in_loop_zero() {
; CHECK-LABEL: bfis_in_loop_zero:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adrp x8, :got:global
; CHECK-NEXT: mov x0, xzr
; CHECK-NEXT: mov w9, wzr
; CHECK-NEXT: ldr x8, [x8, :got_lo12:global]
; CHECK-NEXT: ldr x8, [x8]
; CHECK-NEXT: .LBB0_1: // %midblock
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldrh w10, [x8, #72]
; CHECK-NEXT: ldr x13, [x8, #8]
; CHECK-NEXT: lsr w11, w10, #8
; CHECK-NEXT: cmp w10, #0
; CHECK-NEXT: ldr x8, [x13, #16]
; CHECK-NEXT: cset w12, ne
; CHECK-NEXT: csel w9, w9, w11, eq
; CHECK-NEXT: and x11, x0, #0xffffffff00000000
; CHECK-NEXT: bfi w10, w9, #8, #24
; CHECK-NEXT: orr x11, x11, x12, lsl #16
; CHECK-NEXT: orr x0, x11, x10
; CHECK-NEXT: cbnz x13, .LBB0_1
; CHECK-NEXT: adrp x9, :got:global
; CHECK-NEXT: mov x0, xzr
; CHECK-NEXT: mov w8, wzr
; CHECK-NEXT: ldr x9, [x9, :got_lo12:global]
; CHECK-NEXT: mov w10, #65536 // =0x10000
; CHECK-NEXT: ldr x9, [x9]
; CHECK-NEXT: .LBB0_1: // %midblock
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldrh w11, [x9, #72]
; CHECK-NEXT: and x13, x0, #0xffffffff00000000
; CHECK-NEXT: lsr w12, w11, #8
; CHECK-NEXT: cmp w11, #0
; CHECK-NEXT: csel w8, w8, w12, eq
; CHECK-NEXT: ldr x12, [x9, #8]
; CHECK-NEXT: csel x9, xzr, x10, eq
; CHECK-NEXT: bfi w11, w8, #8, #24
; CHECK-NEXT: orr x13, x9, x13
; CHECK-NEXT: ldr x9, [x12, #16]
; CHECK-NEXT: orr x0, x13, x11
; CHECK-NEXT: cbnz x12, .LBB0_1
; CHECK-NEXT: // %bb.2: // %exit
; CHECK-NEXT: ret
entry:
Expand Down Expand Up @@ -80,25 +81,26 @@ exit:
define i64 @bfis_in_loop_undef() {
; CHECK-LABEL: bfis_in_loop_undef:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adrp x9, :got:global
; CHECK-NEXT: mov w8, wzr
; CHECK-NEXT: // implicit-def: $x0
; CHECK-NEXT: ldr x9, [x9, :got_lo12:global]
; CHECK-NEXT: ldr x9, [x9]
; CHECK-NEXT: .LBB1_1: // %midblock
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldrh w10, [x9, #72]
; CHECK-NEXT: ldr x13, [x9, #8]
; CHECK-NEXT: lsr w11, w10, #8
; CHECK-NEXT: cmp w10, #0
; CHECK-NEXT: ldr x9, [x13, #16]
; CHECK-NEXT: cset w12, ne
; CHECK-NEXT: csel w8, w8, w11, eq
; CHECK-NEXT: and x11, x0, #0xffffffff00000000
; CHECK-NEXT: bfi w10, w8, #8, #24
; CHECK-NEXT: orr x11, x11, x12, lsl #16
; CHECK-NEXT: orr x0, x11, x10
; CHECK-NEXT: cbnz x13, .LBB1_1
; CHECK-NEXT: adrp x9, :got:global
; CHECK-NEXT: mov w8, wzr
; CHECK-NEXT: // implicit-def: $x0
; CHECK-NEXT: ldr x9, [x9, :got_lo12:global]
; CHECK-NEXT: ldr x10, [x9]
; CHECK-NEXT: mov w9, #65536 // =0x10000
; CHECK-NEXT: .LBB1_1: // %midblock
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldrh w11, [x10, #72]
; CHECK-NEXT: and x13, x0, #0xffffffff00000000
; CHECK-NEXT: lsr w12, w11, #8
; CHECK-NEXT: cmp w11, #0
; CHECK-NEXT: csel w8, w8, w12, eq
; CHECK-NEXT: ldr x12, [x10, #8]
; CHECK-NEXT: csel x10, xzr, x9, eq
; CHECK-NEXT: bfi w11, w8, #8, #24
; CHECK-NEXT: orr x13, x10, x13
; CHECK-NEXT: ldr x10, [x12, #16]
; CHECK-NEXT: orr x0, x13, x11
; CHECK-NEXT: cbnz x12, .LBB1_1
; CHECK-NEXT: // %bb.2: // %exit
; CHECK-NEXT: ret
entry:
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/AArch64/select_cc.ll
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Expand Up @@ -6,8 +6,8 @@ define i64 @select_ogt_float(float %a, float %b) {
; CHECK-SD-LABEL: select_ogt_float:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: fcmp s0, s1
; CHECK-SD-NEXT: cset w8, gt
; CHECK-SD-NEXT: ubfiz x0, x8, #2, #32
; CHECK-SD-NEXT: mov w8, #4 // =0x4
; CHECK-SD-NEXT: csel x0, x8, xzr, gt
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: select_ogt_float:
Expand All @@ -26,8 +26,8 @@ define i64 @select_ule_float_inverse(float %a, float %b) {
; CHECK-SD-LABEL: select_ule_float_inverse:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: fcmp s0, s1
; CHECK-SD-NEXT: cset w8, gt
; CHECK-SD-NEXT: ubfiz x0, x8, #2, #32
; CHECK-SD-NEXT: mov w8, #4 // =0x4
; CHECK-SD-NEXT: csel x0, xzr, x8, le
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: select_ule_float_inverse:
Expand All @@ -45,9 +45,9 @@ entry:
define i64 @select_eq_i32(i32 %a, i32 %b) {
; CHECK-SD-LABEL: select_eq_i32:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: mov w8, #4 // =0x4
; CHECK-SD-NEXT: cmp w0, w1
; CHECK-SD-NEXT: cset w8, eq
; CHECK-SD-NEXT: ubfiz x0, x8, #2, #32
; CHECK-SD-NEXT: csel x0, x8, xzr, eq
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: select_eq_i32:
Expand All @@ -65,9 +65,9 @@ entry:
define i64 @select_ne_i32_inverse(i32 %a, i32 %b) {
; CHECK-SD-LABEL: select_ne_i32_inverse:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: mov w8, #4 // =0x4
; CHECK-SD-NEXT: cmp w0, w1
; CHECK-SD-NEXT: cset w8, eq
; CHECK-SD-NEXT: ubfiz x0, x8, #2, #32
; CHECK-SD-NEXT: csel x0, xzr, x8, ne
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: select_ne_i32_inverse:
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/AArch64/selectopt-const.ll
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Expand Up @@ -13,24 +13,24 @@ define i32 @test_const(ptr %in1, ptr %in2, ptr %out, i32 %n, ptr %tbl) {
; CHECK-NEXT: mov w8, w3
; CHECK-NEXT: movk w9, #16309, lsl #16
; CHECK-NEXT: fmov s0, w9
; CHECK-NEXT: mov w9, #16 // =0x10
; CHECK-NEXT: .p2align 5, , 16
; CHECK-NEXT: .LBB0_2: // %for.body
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldr s4, [x1], #4
; CHECK-NEXT: ldr w9, [x0], #4
; CHECK-NEXT: add w9, w9, #10
; CHECK-NEXT: scvtf d3, w9
; CHECK-NEXT: ldr w10, [x0], #4
; CHECK-NEXT: add w10, w10, #10
; CHECK-NEXT: scvtf d3, w10
; CHECK-NEXT: fmadd s4, s4, s0, s1
; CHECK-NEXT: fabs s4, s4
; CHECK-NEXT: fcvt d4, s4
; CHECK-NEXT: fdiv d3, d3, d4
; CHECK-NEXT: fcmp d3, d2
; CHECK-NEXT: cset w9, lt
; CHECK-NEXT: csel x10, x9, xzr, lt
; CHECK-NEXT: subs x8, x8, #1
; CHECK-NEXT: ubfiz x9, x9, #4, #32
; CHECK-NEXT: ldr s3, [x4, x9]
; CHECK-NEXT: fcvtzs w9, s3
; CHECK-NEXT: str w9, [x2], #4
; CHECK-NEXT: ldr s3, [x4, x10]
; CHECK-NEXT: fcvtzs w10, s3
; CHECK-NEXT: str w10, [x2], #4
; CHECK-NEXT: b.ne .LBB0_2
; CHECK-NEXT: .LBB0_3: // %for.cond.cleanup
; CHECK-NEXT: mov w0, wzr
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AMDGPU/amdgcn.private-memory.ll
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Expand Up @@ -19,8 +19,8 @@ declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
; GCN-ALLOCA: v_add_{{[iu]}}32_e32 [[RESULT:v[0-9]+]], vcc, v{{[0-9]+}}, v0

; GCN-PROMOTE: s_cmp_eq_u32 [[IN]], 1
; GCN-PROMOTE-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-PROMOTE-NEXT: v_addc_u32_e32 [[RESULT:v[0-9]+]], vcc, 0, v0, vcc
; GCN-PROMOTE-NEXT: s_cselect_b32 [[SCC:s[0-9]+]], 1, 0
; GCN-PROMOTE-NEXT: v_add_{{[iu]}}32_e32 [[RESULT:v[0-9]+]], vcc, [[SCC]], v0

; GCN: buffer_store_dword [[RESULT]]
define amdgpu_kernel void @work_item_info(ptr addrspace(1) %out, i32 %in) {
Expand Down
19 changes: 7 additions & 12 deletions llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
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Expand Up @@ -82,17 +82,16 @@ define float @test_pow_fast_f32__integral_y(float %x, i32 %y.i) {
; CHECK-NEXT: v_cvt_f32_i32_e32 v1, v1
; CHECK-NEXT: s_mov_b32 s4, 0x800000
; CHECK-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 32, vcc
; CHECK-NEXT: v_cvt_i32_f32_e32 v1, v1
; CHECK-NEXT: v_lshlrev_b32_e32 v3, 5, v3
; CHECK-NEXT: v_ldexp_f32 v3, |v0|, v3
; CHECK-NEXT: v_log_f32_e32 v3, v3
; CHECK-NEXT: v_cvt_f32_i32_e32 v4, v1
; CHECK-NEXT: v_mov_b32_e32 v2, 0x42000000
; CHECK-NEXT: v_cvt_f32_i32_e32 v4, v1
; CHECK-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
; CHECK-NEXT: v_sub_f32_e32 v2, v3, v2
; CHECK-NEXT: v_mul_f32_e32 v3, v2, v4
; CHECK-NEXT: s_mov_b32 s4, 0xc2fc0000
; CHECK-NEXT: v_mul_f32_e32 v3, v2, v4
; CHECK-NEXT: v_mov_b32_e32 v5, 0x42800000
; CHECK-NEXT: v_cmp_gt_f32_e32 vcc, s4, v3
; CHECK-NEXT: v_cndmask_b32_e32 v3, 0, v5, vcc
Expand Down Expand Up @@ -228,8 +227,7 @@ define float @test_powr_fast_f32(float %x, float %y) {
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_mov_b32 s4, 0x800000
; CHECK-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; CHECK-NEXT: v_lshlrev_b32_e32 v3, 5, v3
; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 32, vcc
; CHECK-NEXT: v_ldexp_f32 v0, v0, v3
; CHECK-NEXT: v_log_f32_e32 v0, v0
; CHECK-NEXT: v_mov_b32_e32 v2, 0x42000000
Expand Down Expand Up @@ -368,8 +366,7 @@ define float @test_pown_fast_f32(float %x, i32 %y) {
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_mov_b32 s4, 0x800000
; CHECK-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; CHECK-NEXT: v_lshlrev_b32_e32 v3, 5, v3
; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 32, vcc
; CHECK-NEXT: v_ldexp_f32 v3, |v0|, v3
; CHECK-NEXT: v_log_f32_e32 v3, v3
; CHECK-NEXT: v_cvt_f32_i32_e32 v4, v1
Expand Down Expand Up @@ -511,8 +508,7 @@ define float @test_pown_fast_f32_known_even(float %x, i32 %y.arg) {
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_mov_b32 s4, 0x800000
; CHECK-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; CHECK-NEXT: v_lshlrev_b32_e32 v3, 5, v3
; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 32, vcc
; CHECK-NEXT: v_ldexp_f32 v0, |v0|, v3
; CHECK-NEXT: v_lshlrev_b32_e32 v1, 1, v1
; CHECK-NEXT: v_log_f32_e32 v0, v0
Expand Down Expand Up @@ -651,8 +647,7 @@ define float @test_pown_fast_f32_known_odd(float %x, i32 %y.arg) {
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_mov_b32 s4, 0x800000
; CHECK-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; CHECK-NEXT: v_lshlrev_b32_e32 v3, 5, v3
; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 32, vcc
; CHECK-NEXT: v_ldexp_f32 v3, |v0|, v3
; CHECK-NEXT: v_or_b32_e32 v1, 1, v1
; CHECK-NEXT: v_log_f32_e32 v3, v3
Expand Down
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