[CodeGen] Remove static member function Register::virtReg2Index. NFC #127962
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Use the nonstatic member instead. I'm pretty sure the code in SPRIV is a layering violation. MC layer files are using a CodeGen header.
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@llvm/pr-subscribers-backend-webassembly @llvm/pr-subscribers-backend-spir-v Author: Craig Topper (topperc) ChangesUse the nonstatic member instead. I'm pretty sure the code in SPRIV is a layering violation. MC layer files are using a CodeGen header. Full diff: https://github.com/llvm/llvm-project/pull/127962.diff 12 Files Affected:
diff --git a/llvm/include/llvm/CodeGen/Register.h b/llvm/include/llvm/CodeGen/Register.h
index b5ffe079de123..2fdc2148ef020 100644
--- a/llvm/include/llvm/CodeGen/Register.h
+++ b/llvm/include/llvm/CodeGen/Register.h
@@ -60,13 +60,6 @@ class Register {
return Reg & MCRegister::VirtualRegFlag;
}
- /// Convert a virtual register number to a 0-based index.
- /// The first virtual register in a function will get the index 0.
- static unsigned virtReg2Index(Register Reg) {
- assert(Reg.isVirtual() && "Not a virtual register");
- return Reg.id() & ~MCRegister::VirtualRegFlag;
- }
-
/// Convert a 0-based index to a virtual register number.
/// This is the inverse operation of VirtReg2IndexFunctor below.
static Register index2VirtReg(unsigned Index) {
@@ -84,7 +77,10 @@ class Register {
/// Convert a virtual register number to a 0-based index. The first virtual
/// register in a function will get the index 0.
- unsigned virtRegIndex() const { return virtReg2Index(Reg); }
+ unsigned virtRegIndex() const {
+ assert(isVirtual() && "Not a virtual register");
+ return Reg & ~MCRegister::VirtualRegFlag;
+ }
/// Compute the frame index from a register value representing a stack slot.
int stackSlotIndex() const {
diff --git a/llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h b/llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h
index aaa10e684687c..7c534805b8333 100644
--- a/llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h
+++ b/llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h
@@ -59,7 +59,7 @@ namespace llvm {
: VirtReg(VReg), LaneMask(LaneMask), SU(SU) {}
unsigned getSparseSetIndex() const {
- return Register::virtReg2Index(VirtReg);
+ return Register(VirtReg).virtRegIndex();
}
};
diff --git a/llvm/lib/CodeGen/DetectDeadLanes.cpp b/llvm/lib/CodeGen/DetectDeadLanes.cpp
index a6d2640ed044f..301cb6e1a2d18 100644
--- a/llvm/lib/CodeGen/DetectDeadLanes.cpp
+++ b/llvm/lib/CodeGen/DetectDeadLanes.cpp
@@ -276,7 +276,7 @@ LaneBitmask DeadLaneDetector::determineInitialDefinedLanes(unsigned Reg) {
if (lowersToCopies(DefMI)) {
// Start optimisatically with no used or defined lanes for copy
// instructions. The following dataflow analysis will add more bits.
- unsigned RegIdx = Register::virtReg2Index(Reg);
+ unsigned RegIdx = Register(Reg).virtRegIndex();
DefinedByCopy.set(RegIdx);
PutInWorklist(RegIdx);
diff --git a/llvm/lib/CodeGen/TargetRegisterInfo.cpp b/llvm/lib/CodeGen/TargetRegisterInfo.cpp
index e735c904e1b60..3fe8d5dbc4b67 100644
--- a/llvm/lib/CodeGen/TargetRegisterInfo.cpp
+++ b/llvm/lib/CodeGen/TargetRegisterInfo.cpp
@@ -161,7 +161,7 @@ Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI) {
Printable printVRegOrUnit(unsigned Unit, const TargetRegisterInfo *TRI) {
return Printable([Unit, TRI](raw_ostream &OS) {
if (Register::isVirtualRegister(Unit)) {
- OS << '%' << Register::virtReg2Index(Unit);
+ OS << '%' << Register(Unit).virtRegIndex();
} else {
OS << printRegUnit(Unit, TRI);
}
diff --git a/llvm/lib/Target/Hexagon/BitTracker.cpp b/llvm/lib/Target/Hexagon/BitTracker.cpp
index 4d5789a3c5fe1..8e88f45aeafe5 100644
--- a/llvm/lib/Target/Hexagon/BitTracker.cpp
+++ b/llvm/lib/Target/Hexagon/BitTracker.cpp
@@ -84,7 +84,7 @@ namespace {
raw_ostream &operator<< (raw_ostream &OS, const printv &PV) {
if (PV.R)
- OS << 'v' << Register::virtReg2Index(PV.R);
+ OS << 'v' << Register(PV.R).virtRegIndex();
else
OS << 's';
return OS;
diff --git a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
index 67d822a67e53c..2ee537d2193b3 100644
--- a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
@@ -176,7 +176,7 @@ namespace {
}
static inline unsigned v2x(unsigned v) {
- return Register::virtReg2Index(v);
+ return Register(v).virtRegIndex();
}
static inline unsigned x2v(unsigned x) {
diff --git a/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp b/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
index 5e52cf03cfbc7..cc9485789d211 100644
--- a/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
@@ -167,7 +167,7 @@ namespace {
}
static inline unsigned v2x(unsigned v) {
- return Register::virtReg2Index(v);
+ return Register(v).virtRegIndex();
}
static inline unsigned x2v(unsigned x) {
@@ -271,7 +271,7 @@ namespace {
CellMapShadow(const BitTracker &T) : BT(T) {}
const BitTracker::RegisterCell &lookup(unsigned VR) {
- unsigned RInd = Register::virtReg2Index(VR);
+ unsigned RInd = Register(VR).virtRegIndex();
// Grow the vector to at least 32 elements.
if (RInd >= CVect.size())
CVect.resize(std::max(RInd+16, 32U), nullptr);
@@ -1578,7 +1578,7 @@ bool HexagonGenInsert::runOnMachineFunction(MachineFunction &MF) {
IterListType Out;
for (IFMapType::iterator I = IFMap.begin(), E = IFMap.end(); I != E; ++I) {
- unsigned Idx = Register::virtReg2Index(I->first);
+ unsigned Idx = Register(I->first).virtRegIndex();
if (Idx >= Cutoff)
Out.push_back(I);
}
diff --git a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
index 2ee0c79b8f7c1..10f4ea99fab32 100644
--- a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
+++ b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
@@ -336,7 +336,7 @@ void SPIRVInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
if (OpNo < MI->getNumOperands()) {
const MCOperand &Op = MI->getOperand(OpNo);
if (Op.isReg())
- O << '%' << (Register::virtReg2Index(Op.getReg()) + 1);
+ O << '%' << (Register(Op.getReg()).virtRegIndex() + 1);
else if (Op.isImm())
O << formatImm((int64_t)Op.getImm());
else if (Op.isDFPImm())
diff --git a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp
index 68cc6a3a7aac1..db8287c4b1e02 100644
--- a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp
+++ b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp
@@ -77,7 +77,7 @@ static void emitOperand(const MCOperand &Op, SmallVectorImpl<char> &CB) {
if (Op.isReg()) {
// Emit the id index starting at 1 (0 is an invalid index).
support::endian::write<uint32_t>(
- CB, Register::virtReg2Index(Op.getReg()) + 1, llvm::endianness::little);
+ CB, Register(Op.getReg()).virtRegIndex() + 1, llvm::endianness::little);
} else if (Op.isImm()) {
support::endian::write(CB, static_cast<uint32_t>(Op.getImm()),
llvm::endianness::little);
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp
index 5c1f036abef5a..2662241ef8499 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp
@@ -65,7 +65,7 @@ static void checkFrameBase(WebAssemblyFunctionInfo &MFI, unsigned Local,
if (MFI.isFrameBaseVirtual() && Reg == MFI.getFrameBaseVreg()) {
LLVM_DEBUG({
dbgs() << "Allocating local " << Local << "for VReg "
- << Register::virtReg2Index(Reg) << '\n';
+ << Register(Reg).virtRegIndex() << '\n';
});
MFI.setFrameBaseLocal(Local);
}
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h b/llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h
index 6c9824bbd5d91..8c9fcdee3375a 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h
@@ -121,18 +121,18 @@ class WebAssemblyFunctionInfo final : public MachineFunctionInfo {
void stackifyVReg(MachineRegisterInfo &MRI, unsigned VReg) {
assert(MRI.getUniqueVRegDef(VReg));
- auto I = Register::virtReg2Index(VReg);
+ auto I = Register(VReg).virtRegIndex();
if (I >= VRegStackified.size())
VRegStackified.resize(I + 1);
VRegStackified.set(I);
}
void unstackifyVReg(unsigned VReg) {
- auto I = Register::virtReg2Index(VReg);
+ auto I = Register(VReg).virtRegIndex();
if (I < VRegStackified.size())
VRegStackified.reset(I);
}
bool isVRegStackified(unsigned VReg) const {
- auto I = Register::virtReg2Index(VReg);
+ auto I = Register(VReg).virtRegIndex();
if (I >= VRegStackified.size())
return false;
return VRegStackified.test(I);
@@ -141,12 +141,12 @@ class WebAssemblyFunctionInfo final : public MachineFunctionInfo {
void initWARegs(MachineRegisterInfo &MRI);
void setWAReg(unsigned VReg, unsigned WAReg) {
assert(WAReg != WebAssembly::UnusedReg);
- auto I = Register::virtReg2Index(VReg);
+ auto I = Register(VReg).virtRegIndex();
assert(I < WARegs.size());
WARegs[I] = WAReg;
}
unsigned getWAReg(unsigned VReg) const {
- auto I = Register::virtReg2Index(VReg);
+ auto I = Register(VReg).virtRegIndex();
assert(I < WARegs.size());
return WARegs[I];
}
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyReplacePhysRegs.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyReplacePhysRegs.cpp
index 1e2bee7a5c73b..cb152f500436a 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyReplacePhysRegs.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyReplacePhysRegs.cpp
@@ -93,7 +93,7 @@ bool WebAssemblyReplacePhysRegs::runOnMachineFunction(MachineFunction &MF) {
FI->setFrameBaseVreg(VReg);
LLVM_DEBUG({
dbgs() << "replacing preg " << PReg << " with " << VReg << " ("
- << Register::virtReg2Index(VReg) << ")\n";
+ << Register(VReg).virtRegIndex() << ")\n";
});
}
}
|
arsenm
approved these changes
Feb 20, 2025
| @@ -77,7 +77,7 @@ static void emitOperand(const MCOperand &Op, SmallVectorImpl<char> &CB) { | |||
| if (Op.isReg()) { | |||
| // Emit the id index starting at 1 (0 is an invalid index). | |||
| support::endian::write<uint32_t>( | |||
| CB, Register::virtReg2Index(Op.getReg()) + 1, llvm::endianness::little); | |||
| CB, Register(Op.getReg()).virtRegIndex() + 1, llvm::endianness::little); | |||
| @@ -93,7 +93,7 @@ bool WebAssemblyReplacePhysRegs::runOnMachineFunction(MachineFunction &MF) { | |||
| FI->setFrameBaseVreg(VReg); | |||
| LLVM_DEBUG({ | |||
| dbgs() << "replacing preg " << PReg << " with " << VReg << " (" | |||
| << Register::virtReg2Index(VReg) << ")\n"; | |||
| << Register(VReg).virtRegIndex() << ")\n"; | |||
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Use the nonstatic member instead.
I'm pretty sure the code in SPRIV is a layering violation. MC layer files are using a CodeGen header.