[NVPTX] Remove redundant addressing mode instrs #128044
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@llvm/pr-subscribers-backend-nvptx Author: Alex MacLean (AlexMaclean) ChangesRemove load and store instructions which do not include an immediate, and just use the immediate variants in all cases. These variants will be emitted exactly the same when the immediate offset is 0. Removing the non-immediate versions allows for the removal of a lot of code and would make any MachineIR passes simpler. Patch is 41.91 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/128044.diff 6 Files Affected:
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
index e96c1758676a1..6e990058958e0 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
@@ -13,8 +13,10 @@
#include "NVPTXISelDAGToDAG.h"
#include "NVPTX.h"
#include "NVPTXUtilities.h"
+#include "llvm/ADT/APInt.h"
#include "llvm/Analysis/ValueTracking.h"
#include "llvm/CodeGen/ISDOpcodes.h"
+#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/IR/Instructions.h"
@@ -964,7 +966,6 @@ bool NVPTXDAGToDAGISel::tryLoad(SDNode *N) {
// Create the machine instruction DAG
SDValue N1 = N->getOperand(1);
- SDValue Addr;
SDValue Offset, Base;
std::optional<unsigned> Opcode;
MVT::SimpleValueType TargetVT = LD->getSimpleValueType(0).SimpleTy;
@@ -974,23 +975,17 @@ bool NVPTXDAGToDAGISel::tryLoad(SDNode *N) {
getI32Imm(VecType, DL), getI32Imm(FromType, DL),
getI32Imm(FromTypeWidth, DL)});
- if (SelectDirectAddr(N1, Addr)) {
- Opcode = pickOpcodeForVT(TargetVT, NVPTX::LD_i8_avar, NVPTX::LD_i16_avar,
- NVPTX::LD_i32_avar, NVPTX::LD_i64_avar,
- NVPTX::LD_f32_avar, NVPTX::LD_f64_avar);
- if (!Opcode)
- return false;
- Ops.append({Addr, Chain});
- } else if (PointerSize == 64 ? SelectADDRsi64(N1.getNode(), N1, Base, Offset)
- : SelectADDRsi(N1.getNode(), N1, Base, Offset)) {
+ if (SelectADDRsi(N1.getNode(), N1, Base, Offset)) {
Opcode = pickOpcodeForVT(TargetVT, NVPTX::LD_i8_asi, NVPTX::LD_i16_asi,
NVPTX::LD_i32_asi, NVPTX::LD_i64_asi,
NVPTX::LD_f32_asi, NVPTX::LD_f64_asi);
if (!Opcode)
return false;
Ops.append({Base, Offset, Chain});
- } else if (PointerSize == 64 ? SelectADDRri64(N1.getNode(), N1, Base, Offset)
- : SelectADDRri(N1.getNode(), N1, Base, Offset)) {
+ } else {
+ PointerSize == 64 ? SelectADDRri64(N1.getNode(), N1, Base, Offset)
+ : SelectADDRri(N1.getNode(), N1, Base, Offset);
+
if (PointerSize == 64)
Opcode =
pickOpcodeForVT(TargetVT, NVPTX::LD_i8_ari_64, NVPTX::LD_i16_ari_64,
@@ -1003,19 +998,6 @@ bool NVPTXDAGToDAGISel::tryLoad(SDNode *N) {
if (!Opcode)
return false;
Ops.append({Base, Offset, Chain});
- } else {
- if (PointerSize == 64)
- Opcode =
- pickOpcodeForVT(TargetVT, NVPTX::LD_i8_areg_64, NVPTX::LD_i16_areg_64,
- NVPTX::LD_i32_areg_64, NVPTX::LD_i64_areg_64,
- NVPTX::LD_f32_areg_64, NVPTX::LD_f64_areg_64);
- else
- Opcode = pickOpcodeForVT(TargetVT, NVPTX::LD_i8_areg, NVPTX::LD_i16_areg,
- NVPTX::LD_i32_areg, NVPTX::LD_i64_areg,
- NVPTX::LD_f32_areg, NVPTX::LD_f64_areg);
- if (!Opcode)
- return false;
- Ops.append({N1, Chain});
}
SDNode *NVPTXLD =
@@ -1102,7 +1084,7 @@ bool NVPTXDAGToDAGISel::tryLoadVector(SDNode *N) {
}
SDValue Op1 = N->getOperand(1);
- SDValue Addr, Offset, Base;
+ SDValue Offset, Base;
std::optional<unsigned> Opcode;
SDNode *LD;
@@ -1111,29 +1093,7 @@ bool NVPTXDAGToDAGISel::tryLoadVector(SDNode *N) {
getI32Imm(VecType, DL), getI32Imm(FromType, DL),
getI32Imm(FromTypeWidth, DL)});
- if (SelectDirectAddr(Op1, Addr)) {
- switch (N->getOpcode()) {
- default:
- return false;
- case NVPTXISD::LoadV2:
- Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
- NVPTX::LDV_i8_v2_avar, NVPTX::LDV_i16_v2_avar,
- NVPTX::LDV_i32_v2_avar, NVPTX::LDV_i64_v2_avar,
- NVPTX::LDV_f32_v2_avar, NVPTX::LDV_f64_v2_avar);
- break;
- case NVPTXISD::LoadV4:
- Opcode =
- pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, NVPTX::LDV_i8_v4_avar,
- NVPTX::LDV_i16_v4_avar, NVPTX::LDV_i32_v4_avar,
- std::nullopt, NVPTX::LDV_f32_v4_avar, std::nullopt);
- break;
- }
- if (!Opcode)
- return false;
- Ops.append({Addr, Chain});
- } else if (PointerSize == 64
- ? SelectADDRsi64(Op1.getNode(), Op1, Base, Offset)
- : SelectADDRsi(Op1.getNode(), Op1, Base, Offset)) {
+ if (SelectADDRsi(Op1.getNode(), Op1, Base, Offset)) {
switch (N->getOpcode()) {
default:
return false;
@@ -1153,9 +1113,10 @@ bool NVPTXDAGToDAGISel::tryLoadVector(SDNode *N) {
if (!Opcode)
return false;
Ops.append({Base, Offset, Chain});
- } else if (PointerSize == 64
- ? SelectADDRri64(Op1.getNode(), Op1, Base, Offset)
- : SelectADDRri(Op1.getNode(), Op1, Base, Offset)) {
+ } else {
+ PointerSize == 64 ? SelectADDRri64(Op1.getNode(), Op1, Base, Offset)
+ : SelectADDRri(Op1.getNode(), Op1, Base, Offset);
+
if (PointerSize == 64) {
switch (N->getOpcode()) {
default:
@@ -1195,47 +1156,6 @@ bool NVPTXDAGToDAGISel::tryLoadVector(SDNode *N) {
if (!Opcode)
return false;
Ops.append({Base, Offset, Chain});
- } else {
- if (PointerSize == 64) {
- switch (N->getOpcode()) {
- default:
- return false;
- case NVPTXISD::LoadV2:
- Opcode = pickOpcodeForVT(
- EltVT.getSimpleVT().SimpleTy, NVPTX::LDV_i8_v2_areg_64,
- NVPTX::LDV_i16_v2_areg_64, NVPTX::LDV_i32_v2_areg_64,
- NVPTX::LDV_i64_v2_areg_64, NVPTX::LDV_f32_v2_areg_64,
- NVPTX::LDV_f64_v2_areg_64);
- break;
- case NVPTXISD::LoadV4:
- Opcode = pickOpcodeForVT(
- EltVT.getSimpleVT().SimpleTy, NVPTX::LDV_i8_v4_areg_64,
- NVPTX::LDV_i16_v4_areg_64, NVPTX::LDV_i32_v4_areg_64, std::nullopt,
- NVPTX::LDV_f32_v4_areg_64, std::nullopt);
- break;
- }
- } else {
- switch (N->getOpcode()) {
- default:
- return false;
- case NVPTXISD::LoadV2:
- Opcode =
- pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, NVPTX::LDV_i8_v2_areg,
- NVPTX::LDV_i16_v2_areg, NVPTX::LDV_i32_v2_areg,
- NVPTX::LDV_i64_v2_areg, NVPTX::LDV_f32_v2_areg,
- NVPTX::LDV_f64_v2_areg);
- break;
- case NVPTXISD::LoadV4:
- Opcode =
- pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, NVPTX::LDV_i8_v4_areg,
- NVPTX::LDV_i16_v4_areg, NVPTX::LDV_i32_v4_areg,
- std::nullopt, NVPTX::LDV_f32_v4_areg, std::nullopt);
- break;
- }
- }
- if (!Opcode)
- return false;
- Ops.append({Op1, Chain});
}
LD = CurDAG->getMachineNode(*Opcode, DL, N->getVTList(), Ops);
@@ -1344,8 +1264,10 @@ bool NVPTXDAGToDAGISel::tryLDGLDU(SDNode *N) {
return false;
SDValue Ops[] = { Addr, Chain };
LD = CurDAG->getMachineNode(*Opcode, DL, InstVTList, Ops);
- } else if (TM.is64Bit() ? SelectADDRri64(Op1.getNode(), Op1, Base, Offset)
- : SelectADDRri(Op1.getNode(), Op1, Base, Offset)) {
+ } else {
+ TM.is64Bit() ? SelectADDRri64(Op1.getNode(), Op1, Base, Offset)
+ : SelectADDRri(Op1.getNode(), Op1, Base, Offset);
+
if (TM.is64Bit()) {
switch (N->getOpcode()) {
default:
@@ -1457,122 +1379,6 @@ bool NVPTXDAGToDAGISel::tryLDGLDU(SDNode *N) {
return false;
SDValue Ops[] = {Base, Offset, Chain};
LD = CurDAG->getMachineNode(*Opcode, DL, InstVTList, Ops);
- } else {
- if (TM.is64Bit()) {
- switch (N->getOpcode()) {
- default:
- return false;
- case ISD::LOAD:
- Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
- NVPTX::INT_PTX_LDG_GLOBAL_i8areg64,
- NVPTX::INT_PTX_LDG_GLOBAL_i16areg64,
- NVPTX::INT_PTX_LDG_GLOBAL_i32areg64,
- NVPTX::INT_PTX_LDG_GLOBAL_i64areg64,
- NVPTX::INT_PTX_LDG_GLOBAL_f32areg64,
- NVPTX::INT_PTX_LDG_GLOBAL_f64areg64);
- break;
- case ISD::INTRINSIC_W_CHAIN:
- Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
- NVPTX::INT_PTX_LDU_GLOBAL_i8areg64,
- NVPTX::INT_PTX_LDU_GLOBAL_i16areg64,
- NVPTX::INT_PTX_LDU_GLOBAL_i32areg64,
- NVPTX::INT_PTX_LDU_GLOBAL_i64areg64,
- NVPTX::INT_PTX_LDU_GLOBAL_f32areg64,
- NVPTX::INT_PTX_LDU_GLOBAL_f64areg64);
- break;
- case NVPTXISD::LoadV2:
- Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
- NVPTX::INT_PTX_LDG_G_v2i8_ELE_areg64,
- NVPTX::INT_PTX_LDG_G_v2i16_ELE_areg64,
- NVPTX::INT_PTX_LDG_G_v2i32_ELE_areg64,
- NVPTX::INT_PTX_LDG_G_v2i64_ELE_areg64,
- NVPTX::INT_PTX_LDG_G_v2f32_ELE_areg64,
- NVPTX::INT_PTX_LDG_G_v2f64_ELE_areg64);
- break;
- case NVPTXISD::LDUV2:
- Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
- NVPTX::INT_PTX_LDU_G_v2i8_ELE_areg64,
- NVPTX::INT_PTX_LDU_G_v2i16_ELE_areg64,
- NVPTX::INT_PTX_LDU_G_v2i32_ELE_areg64,
- NVPTX::INT_PTX_LDU_G_v2i64_ELE_areg64,
- NVPTX::INT_PTX_LDU_G_v2f32_ELE_areg64,
- NVPTX::INT_PTX_LDU_G_v2f64_ELE_areg64);
- break;
- case NVPTXISD::LoadV4:
- Opcode = pickOpcodeForVT(
- EltVT.getSimpleVT().SimpleTy, NVPTX::INT_PTX_LDG_G_v4i8_ELE_areg64,
- NVPTX::INT_PTX_LDG_G_v4i16_ELE_areg64,
- NVPTX::INT_PTX_LDG_G_v4i32_ELE_areg64, std::nullopt,
- NVPTX::INT_PTX_LDG_G_v4f32_ELE_areg64, std::nullopt);
- break;
- case NVPTXISD::LDUV4:
- Opcode = pickOpcodeForVT(
- EltVT.getSimpleVT().SimpleTy, NVPTX::INT_PTX_LDU_G_v4i8_ELE_areg64,
- NVPTX::INT_PTX_LDU_G_v4i16_ELE_areg64,
- NVPTX::INT_PTX_LDU_G_v4i32_ELE_areg64, std::nullopt,
- NVPTX::INT_PTX_LDU_G_v4f32_ELE_areg64, std::nullopt);
- break;
- }
- } else {
- switch (N->getOpcode()) {
- default:
- return false;
- case ISD::LOAD:
- Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
- NVPTX::INT_PTX_LDG_GLOBAL_i8areg,
- NVPTX::INT_PTX_LDG_GLOBAL_i16areg,
- NVPTX::INT_PTX_LDG_GLOBAL_i32areg,
- NVPTX::INT_PTX_LDG_GLOBAL_i64areg,
- NVPTX::INT_PTX_LDG_GLOBAL_f32areg,
- NVPTX::INT_PTX_LDG_GLOBAL_f64areg);
- break;
- case ISD::INTRINSIC_W_CHAIN:
- Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
- NVPTX::INT_PTX_LDU_GLOBAL_i8areg,
- NVPTX::INT_PTX_LDU_GLOBAL_i16areg,
- NVPTX::INT_PTX_LDU_GLOBAL_i32areg,
- NVPTX::INT_PTX_LDU_GLOBAL_i64areg,
- NVPTX::INT_PTX_LDU_GLOBAL_f32areg,
- NVPTX::INT_PTX_LDU_GLOBAL_f64areg);
- break;
- case NVPTXISD::LoadV2:
- Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
- NVPTX::INT_PTX_LDG_G_v2i8_ELE_areg32,
- NVPTX::INT_PTX_LDG_G_v2i16_ELE_areg32,
- NVPTX::INT_PTX_LDG_G_v2i32_ELE_areg32,
- NVPTX::INT_PTX_LDG_G_v2i64_ELE_areg32,
- NVPTX::INT_PTX_LDG_G_v2f32_ELE_areg32,
- NVPTX::INT_PTX_LDG_G_v2f64_ELE_areg32);
- break;
- case NVPTXISD::LDUV2:
- Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
- NVPTX::INT_PTX_LDU_G_v2i8_ELE_areg32,
- NVPTX::INT_PTX_LDU_G_v2i16_ELE_areg32,
- NVPTX::INT_PTX_LDU_G_v2i32_ELE_areg32,
- NVPTX::INT_PTX_LDU_G_v2i64_ELE_areg32,
- NVPTX::INT_PTX_LDU_G_v2f32_ELE_areg32,
- NVPTX::INT_PTX_LDU_G_v2f64_ELE_areg32);
- break;
- case NVPTXISD::LoadV4:
- Opcode = pickOpcodeForVT(
- EltVT.getSimpleVT().SimpleTy, NVPTX::INT_PTX_LDG_G_v4i8_ELE_areg32,
- NVPTX::INT_PTX_LDG_G_v4i16_ELE_areg32,
- NVPTX::INT_PTX_LDG_G_v4i32_ELE_areg32, std::nullopt,
- NVPTX::INT_PTX_LDG_G_v4f32_ELE_areg32, std::nullopt);
- break;
- case NVPTXISD::LDUV4:
- Opcode = pickOpcodeForVT(
- EltVT.getSimpleVT().SimpleTy, NVPTX::INT_PTX_LDU_G_v4i8_ELE_areg32,
- NVPTX::INT_PTX_LDU_G_v4i16_ELE_areg32,
- NVPTX::INT_PTX_LDU_G_v4i32_ELE_areg32, std::nullopt,
- NVPTX::INT_PTX_LDU_G_v4f32_ELE_areg32, std::nullopt);
- break;
- }
- }
- if (!Opcode)
- return false;
- SDValue Ops[] = { Op1, Chain };
- LD = CurDAG->getMachineNode(*Opcode, DL, InstVTList, Ops);
}
// For automatic generation of LDG (through SelectLoad[Vector], not the
@@ -1658,7 +1464,6 @@ bool NVPTXDAGToDAGISel::tryStore(SDNode *N) {
// Create the machine instruction DAG
SDValue Value = PlainStore ? PlainStore->getValue() : AtomicStore->getVal();
SDValue BasePtr = ST->getBasePtr();
- SDValue Addr;
SDValue Offset, Base;
std::optional<unsigned> Opcode;
MVT::SimpleValueType SourceVT =
@@ -1669,25 +1474,16 @@ bool NVPTXDAGToDAGISel::tryStore(SDNode *N) {
getI32Imm(CodeAddrSpace, DL), getI32Imm(VecType, DL),
getI32Imm(ToType, DL), getI32Imm(ToTypeWidth, DL)});
- if (SelectDirectAddr(BasePtr, Addr)) {
- Opcode = pickOpcodeForVT(SourceVT, NVPTX::ST_i8_avar, NVPTX::ST_i16_avar,
- NVPTX::ST_i32_avar, NVPTX::ST_i64_avar,
- NVPTX::ST_f32_avar, NVPTX::ST_f64_avar);
- if (!Opcode)
- return false;
- Ops.append({Addr, Chain});
- } else if (PointerSize == 64
- ? SelectADDRsi64(BasePtr.getNode(), BasePtr, Base, Offset)
- : SelectADDRsi(BasePtr.getNode(), BasePtr, Base, Offset)) {
+ if (SelectADDRsi(BasePtr.getNode(), BasePtr, Base, Offset)) {
Opcode = pickOpcodeForVT(SourceVT, NVPTX::ST_i8_asi, NVPTX::ST_i16_asi,
NVPTX::ST_i32_asi, NVPTX::ST_i64_asi,
NVPTX::ST_f32_asi, NVPTX::ST_f64_asi);
if (!Opcode)
return false;
Ops.append({Base, Offset, Chain});
- } else if (PointerSize == 64
- ? SelectADDRri64(BasePtr.getNode(), BasePtr, Base, Offset)
- : SelectADDRri(BasePtr.getNode(), BasePtr, Base, Offset)) {
+ } else {
+ PointerSize == 64 ? SelectADDRri64(BasePtr.getNode(), BasePtr, Base, Offset)
+ : SelectADDRri(BasePtr.getNode(), BasePtr, Base, Offset);
if (PointerSize == 64)
Opcode =
pickOpcodeForVT(SourceVT, NVPTX::ST_i8_ari_64, NVPTX::ST_i16_ari_64,
@@ -1700,19 +1496,6 @@ bool NVPTXDAGToDAGISel::tryStore(SDNode *N) {
if (!Opcode)
return false;
Ops.append({Base, Offset, Chain});
- } else {
- if (PointerSize == 64)
- Opcode =
- pickOpcodeForVT(SourceVT, NVPTX::ST_i8_areg_64, NVPTX::ST_i16_areg_64,
- NVPTX::ST_i32_areg_64, NVPTX::ST_i64_areg_64,
- NVPTX::ST_f32_areg_64, NVPTX::ST_f64_areg_64);
- else
- Opcode = pickOpcodeForVT(SourceVT, NVPTX::ST_i8_areg, NVPTX::ST_i16_areg,
- NVPTX::ST_i32_areg, NVPTX::ST_i64_areg,
- NVPTX::ST_f32_areg, NVPTX::ST_f64_areg);
- if (!Opcode)
- return false;
- Ops.append({BasePtr, Chain});
}
SDNode *NVPTXST = CurDAG->getMachineNode(*Opcode, DL, MVT::Other, Ops);
@@ -1728,7 +1511,7 @@ bool NVPTXDAGToDAGISel::tryStore(SDNode *N) {
bool NVPTXDAGToDAGISel::tryStoreVector(SDNode *N) {
SDValue Op1 = N->getOperand(1);
- SDValue Addr, Offset, Base;
+ SDValue Offset, Base;
std::optional<unsigned> Opcode;
SDNode *ST;
EVT EltVT = Op1.getValueType();
@@ -1785,26 +1568,7 @@ bool NVPTXDAGToDAGISel::tryStoreVector(SDNode *N) {
getI32Imm(CodeAddrSpace, DL), getI32Imm(VecType, DL),
getI32Imm(ToType, DL), getI32Imm(ToTypeWidth, DL)});
- if (SelectDirectAddr(N2, Addr)) {
- switch (N->getOpcode()) {
- default:
- return false;
- case NVPTXISD::StoreV2:
- Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
- NVPTX::STV_i8_v2_avar, NVPTX::STV_i16_v2_avar,
- NVPTX::STV_i32_v2_avar, NVPTX::STV_i64_v2_avar,
- NVPTX::STV_f32_v2_avar, NVPTX::STV_f64_v2_avar);
- break;
- case NVPTXISD::StoreV4:
- Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
- NVPTX::STV_i8_v4_avar, NVPTX::STV_i16_v4_avar,
- NVPTX::STV_i32_v4_avar, std::nullopt,
- NVPTX::STV_f32_v4_avar, std::nullopt);
- break;
- }
- Ops.push_back(Addr);
- } else if (PointerSize == 64 ? SelectADDRsi64(N2.getNode(), N2, Base, Offset)
- : SelectADDRsi(N2.getNode(), N2, Base, Offset)) {
+ if (SelectADDRsi(N2.getNode(), N2, Base, Offset)) {
switch (N->getOpcode()) {
default:
return false;
@@ -1822,8 +1586,10 @@ bool NVPTXDAGToDAGISel::tryStoreVector(SDNode *N) {
break;
}
Ops.append({Base, Offset});
- } else if (PointerSize == 64 ? SelectADDRri64(N2.getNode(), N2, Base, Offset)
- : SelectADDRri(N2.getNode(), N2, Base, Offset)) {
+ } else {
+ PointerSize == 64 ? SelectADDRri64(N2.getNode(), N2, Base, Offset)
+ : SelectADDRri(N2.getNode(), N2, Base, Offset);
+
if (PointerSize == 64) {
switch (N->getOpcode()) {
default:
@@ -1861,47 +1627,7 @@ bool NVPTXDAGToDAGISel::tryStoreVector(SDNode *N) {
}
}
Ops.append({Base, Offset});
- } else {
- if (PointerSize == 64) {
- switch (N->getOpcode()) {
- default:
- return false;
- case NVPTXISD::StoreV2:
- Opcode = pickOpcodeForVT(
- EltVT.getSimpleVT().SimpleTy, NVPTX::STV_i8_v2_areg_64,
- NVPTX::STV_i16_v2_areg_64, NVPTX::STV_i32_v2_areg_64,
- NVPTX::STV_i64_v2_areg_64, NVPTX::STV_f32_v2_areg_64,
- NVPTX::STV_f64_v2_areg_64);
- break;
- case NVPTXISD::StoreV4:
- Opcode = pickOpcodeForVT(
- EltVT.getSimpleVT().SimpleTy, NVPTX::STV_i8_v4_areg_64,
- NVPTX::STV_i16_v4_areg_64, NVPTX::STV_i32_v4_areg_64, std::nullopt,
- NVPTX::STV_f32_v4_areg_64, std::nullopt);
- break;
- }
- } else {
- switch (N->getOpcode()) {
- default:
- return false;
- case NVPTXISD::StoreV2:
- Opcode =
- pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, NVPTX::STV_i8_v2_areg,
- NVPTX::STV_i16_v2_areg, NVPTX::STV_i32_v2_areg,
- NVPTX::STV_i64_v2_areg, NVPTX::STV_f32_v2_areg,
- NVPTX::STV_f64_v2_areg);
- break;
- case NVPTXISD::StoreV4:
- Opcode =
- pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, NVPTX::STV_i8_v4_areg,
- NVPTX::STV_i16_v4_areg, NVPTX::STV_i32_v4_areg,
- std::nullopt, NVPTX::STV_f32_v4_areg, std::nullopt);
...
[truncated]
|
Artem-B
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Artem-B
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Feb 20, 2025
kalxr
approved these changes
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Remove load and store instructions which do not include an immediate, and just use the immediate variants in all cases. These variants will be emitted exactly the same when the immediate offset is 0. Removing the non-immediate versions allows for the removal of a lot of code and would make any MachineIR passes simpler.